phy: qcom-qmp: rename QMP V2 PCS registers

Rename QMP V2 PCS registers to follow the usual pattern of
QPHY_V2_PCS_*.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220705094320.1313312-7-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
index 587ff10e330cf0c303e2db48467ea36bfe6415bc..df1e99ceed17d11f1b4cc3a108ce3458035f3b06 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
@@ -1674,7 +1674,7 @@ static int qcom_qmp_phy_combo_com_init(struct qmp_phy *qphy)
                                cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
                                cfg->pwrdn_ctrl);
        else
-               qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
+               qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
                                cfg->pwrdn_ctrl);
 
        mutex_unlock(&qmp->phy_mutex);
@@ -1836,7 +1836,7 @@ static int qcom_qmp_phy_combo_power_off(struct phy *phy)
                        qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
                                     cfg->pwrdn_ctrl);
                } else {
-                       qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
+                       qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
                                        cfg->pwrdn_ctrl);
                }
        }

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
index 502ea4de3044a1c1a8d6a2a8f588561d8b16bd5e..4b6ddc7ec8623888f5db56900dbc27e1c777454b 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
@@ -222,17 +222,17 @@ static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
 };
 
 static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
-       QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
-       QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
-       QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL, 0x4c),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 
        QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
 
-       QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
-       QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
-       QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
-       QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
-       QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x05),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_DOWN_CONTROL, 0x02),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG4, 0x00),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG1, 0xa3),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
 };
 
 struct qmp_phy;
@@ -637,7 +637,7 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
         * Pull out PHY from POWER DOWN state.
         * This is active low enable signal to power-down PHY.
         */
-       qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
+       qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
 
        if (cfg->has_pwrdn_delay)
                usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
@@ -687,7 +687,7 @@ static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy)
                qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
                             cfg->pwrdn_ctrl);
        } else {
-               qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
+               qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
                                cfg->pwrdn_ctrl);
        }
 

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 5a16aaef3e97274ccba79ab279b790eef2d5c4d7..e3404aa05e13f5a492d1e77a4f101320d9e74e7e 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -438,17 +438,17 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
 };
 
 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
-       QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
-       QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
-       QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
-       QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
-       QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
-       QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
-       QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
        QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
-       QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
-       QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
-       QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe),
        QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
        QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
 };
@@ -1984,7 +1984,7 @@ static int qcom_qmp_phy_pcie_com_init(struct qmp_phy *qphy)
                                cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
                                cfg->pwrdn_ctrl);
        else
-               qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
+               qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
                                cfg->pwrdn_ctrl);
 
        return 0;
@@ -2093,7 +2093,7 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy)
         * Pull out PHY from POWER DOWN state.
         * This is active low enable signal to power-down PHY.
         */
-       qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
+       qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
 
        if (cfg->has_pwrdn_delay)
                usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
@@ -2141,7 +2141,7 @@ static int qcom_qmp_phy_pcie_power_off(struct phy *phy)
                qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
                             cfg->pwrdn_ctrl);
        } else {
-               qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
+               qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
                                cfg->pwrdn_ctrl);
        }
 

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 83330f7ec64c8093e5804b626a7ab37a4fdcb6b3..bfe5f562bcd0d424bbe3835e87c5621f73e9673f 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -310,15 +310,15 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
 };
 
 static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
-       QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
-       QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
-       QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
-       QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
-       QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
-       QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
-       QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
-       QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
-       QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_PWM_GEAR_BAND, 0x15),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_CTRL2, 0x6d),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL, 0x0f),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SYM_RESYNC_CTRL, 0x03),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
 };
 
 static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
@@ -941,7 +941,7 @@ static int qcom_qmp_phy_ufs_com_init(struct qmp_phy *qphy)
                             cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
                             cfg->pwrdn_ctrl);
        else
-               qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
+               qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
                             cfg->pwrdn_ctrl);
 
        return 0;
@@ -1083,7 +1083,7 @@ static int qcom_qmp_phy_ufs_power_off(struct phy *phy)
                qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
                             cfg->pwrdn_ctrl);
        } else {
-               qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
+               qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
                                cfg->pwrdn_ctrl);
        }
 

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
index 597edeb2d8c3dc637a7fd2e07ac8bc0e92be4435..40ac61bcadac0530c60aeb1ccc01ff24077f5c14 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -325,10 +325,10 @@ static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
        QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
 
        /* Lock Det settings */
-       QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
-       QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
-       QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
-       QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG1, 0xd1),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG2, 0x1f),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG3, 0x47),
+       QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG2, 0x08),
 };
 
 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
@@ -2095,7 +2095,7 @@ static int qcom_qmp_phy_usb_com_init(struct qmp_phy *qphy)
                             cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
                             cfg->pwrdn_ctrl);
        else
-               qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
+               qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
                             cfg->pwrdn_ctrl);
 
        return 0;
@@ -2223,7 +2223,7 @@ static int qcom_qmp_phy_usb_power_off(struct phy *phy)
                qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
                             cfg->pwrdn_ctrl);
        } else {
-               qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
+               qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
                                cfg->pwrdn_ctrl);
        }
 

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 6cb660455088a7588bed390b774257e24583141d..64af9720b3f90972204dd527b74f3fffb125a9ba 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -208,33 +208,33 @@
 #define QSERDES_RX_RX_INTERFACE_MODE                   0x12c
 
 /* Only for QMP V2 PHY - PCS registers */
-#define QPHY_POWER_DOWN_CONTROL                                0x04
-#define QPHY_TXDEEMPH_M6DB_V0                          0x24
-#define QPHY_TXDEEMPH_M3P5DB_V0                                0x28
-#define QPHY_TX_LARGE_AMP_DRV_LVL                      0x34
-#define QPHY_TX_LARGE_AMP_POST_EMP_LVL                 0x38
-#define QPHY_TX_SMALL_AMP_DRV_LVL                      0x3c
-#define QPHY_TX_SMALL_AMP_POST_EMP_LVL                 0x40
-#define QPHY_ENDPOINT_REFCLK_DRIVE                     0x54
-#define QPHY_RX_IDLE_DTCT_CNTRL                                0x58
-#define QPHY_POWER_STATE_CONFIG1                       0x60
-#define QPHY_POWER_STATE_CONFIG2                       0x64
-#define QPHY_POWER_STATE_CONFIG4                       0x6c
-#define QPHY_LOCK_DETECT_CONFIG1                       0x80
-#define QPHY_LOCK_DETECT_CONFIG2                       0x84
-#define QPHY_LOCK_DETECT_CONFIG3                       0x88
-#define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK               0xa0
-#define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK                 0xa4
-#define QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP            0xcc
-#define QPHY_RX_SYM_RESYNC_CTRL                                0x13c
-#define QPHY_RX_MIN_HIBERN8_TIME                       0x140
-#define QPHY_RX_SIGDET_CTRL2                           0x148
-#define QPHY_RX_PWM_GEAR_BAND                          0x154
-#define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB          0x1a8
-#define QPHY_OSC_DTCT_ACTIONS                          0x1ac
-#define QPHY_RX_SIGDET_LVL                             0x1d8
-#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB           0x1dc
-#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB           0x1e0
+#define QPHY_V2_PCS_POWER_DOWN_CONTROL                         0x04
+#define QPHY_V2_PCS_TXDEEMPH_M6DB_V0                           0x24
+#define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0                         0x28
+#define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL                       0x34
+#define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL                  0x38
+#define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL                       0x3c
+#define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL                  0x40
+#define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE                      0x54
+#define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL                         0x58
+#define QPHY_V2_PCS_POWER_STATE_CONFIG1                        0x60
+#define QPHY_V2_PCS_POWER_STATE_CONFIG2                        0x64
+#define QPHY_V2_PCS_POWER_STATE_CONFIG4                        0x6c
+#define QPHY_V2_PCS_LOCK_DETECT_CONFIG1                        0x80
+#define QPHY_V2_PCS_LOCK_DETECT_CONFIG2                        0x84
+#define QPHY_V2_PCS_LOCK_DETECT_CONFIG3                        0x88
+#define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK                0xa0
+#define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK                  0xa4
+#define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP             0xcc
+#define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL                         0x13c
+#define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME                        0x140
+#define QPHY_V2_PCS_RX_SIGDET_CTRL2                            0x148
+#define QPHY_V2_PCS_RX_PWM_GEAR_BAND                           0x154
+#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB           0x1a8
+#define QPHY_V2_PCS_OSC_DTCT_ACTIONS                           0x1ac
+#define QPHY_V2_PCS_RX_SIGDET_LVL                              0x1d8
+#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB            0x1dc
+#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB            0x1e0
 
 /* Only for QMP V3 & V4 PHY - DP COM registers */
 #define QPHY_V3_DP_COM_PHY_MODE_CTRL                   0x00