drm/amdgpu: update ib start and size alignment

Update IB starting address alignment and size alignment with correct values
for decode and encode IPs.

Decode IB starting address alignment: 256 bytes
Decode IB size alignment: 64 bytes
Encode IB starting address alignment: 256 bytes
Encode IB size alignment: 4 bytes

Also bump amdgpu driver version for this update.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index d2cf1c39563bed8e5ce796bc8aa1f1e547db9c02..7fd3826c7b92b1e52348c26829ce78f590001a74 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -114,9 +114,10 @@
  *   3.53.0 - Support for GFX11 CP GFX shadowing
  *   3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support
  * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query
+ * - 3.56.0 - Update IB start address and size alignment for decode and encode
  */
 #define KMS_DRIVER_MAJOR       3
-#define KMS_DRIVER_MINOR       55
+#define KMS_DRIVER_MINOR       56
 #define KMS_DRIVER_PATCHLEVEL  0
 
 /*

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 63f608c0bfa9ed24a7e5525e489a09aef16ac5f9..583cf03950cd7fe981e1db8bab1f029dc5b39df8 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -447,7 +447,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
                        if (adev->uvd.inst[i].ring.sched.ready)
                                ++num_rings;
                }
-               ib_start_alignment = 64;
+               ib_start_alignment = 256;
                ib_size_alignment = 64;
                break;
        case AMDGPU_HW_IP_VCE:
@@ -455,8 +455,8 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
                for (i = 0; i < adev->vce.num_rings; i++)
                        if (adev->vce.ring[i].sched.ready)
                                ++num_rings;
-               ib_start_alignment = 4;
-               ib_size_alignment = 1;
+               ib_start_alignment = 256;
+               ib_size_alignment = 4;
                break;
        case AMDGPU_HW_IP_UVD_ENC:
                type = AMD_IP_BLOCK_TYPE_UVD;
@@ -468,8 +468,8 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
                                if (adev->uvd.inst[i].ring_enc[j].sched.ready)
                                        ++num_rings;
                }
-               ib_start_alignment = 64;
-               ib_size_alignment = 64;
+               ib_start_alignment = 256;
+               ib_size_alignment = 4;
                break;
        case AMDGPU_HW_IP_VCN_DEC:
                type = AMD_IP_BLOCK_TYPE_VCN;
@@ -480,8 +480,8 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
                        if (adev->vcn.inst[i].ring_dec.sched.ready)
                                ++num_rings;
                }
-               ib_start_alignment = 16;
-               ib_size_alignment = 16;
+               ib_start_alignment = 256;
+               ib_size_alignment = 64;
                break;
        case AMDGPU_HW_IP_VCN_ENC:
                type = AMD_IP_BLOCK_TYPE_VCN;
@@ -493,8 +493,8 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
                                if (adev->vcn.inst[i].ring_enc[j].sched.ready)
                                        ++num_rings;
                }
-               ib_start_alignment = 64;
-               ib_size_alignment = 1;
+               ib_start_alignment = 256;
+               ib_size_alignment = 4;
                break;
        case AMDGPU_HW_IP_VCN_JPEG:
                type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
@@ -508,8 +508,8 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
                                if (adev->jpeg.inst[i].ring_dec[j].sched.ready)
                                        ++num_rings;
                }
-               ib_start_alignment = 16;
-               ib_size_alignment = 16;
+               ib_start_alignment = 256;
+               ib_size_alignment = 64;
                break;
        case AMDGPU_HW_IP_VPE:
                type = AMD_IP_BLOCK_TYPE_VPE;