arm64: dts: ti: k3-am64: Remove PCIe endpoint node

This node is an example node for the PCIe controller in "endpoint" mode.
By default the controller is in "root complex" mode and there is already a
DT node for the same.

Examples should go in the bindings or other documentation.

Remove this node.

Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20240124183659.149119-4-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index e348114f42e017cfaa3dd02ab20e06e12dfed138..d5938f966a2ddaa63886f415b6eefd0a4450c415 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -1041,25 +1041,6 @@
                status = "disabled";
        };
 
-       pcie0_ep: pcie-ep@f102000 {
-               compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep";
-               reg = <0x00 0x0f102000 0x00 0x1000>,
-                     <0x00 0x0f100000 0x00 0x400>,
-                     <0x00 0x0d000000 0x00 0x00800000>,
-                     <0x00 0x68000000 0x00 0x08000000>;
-               reg-names = "intd_cfg", "user_cfg", "reg", "mem";
-               interrupt-names = "link_state";
-               interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
-               ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
-               max-link-speed = <2>;
-               num-lanes = <1>;
-               power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
-               clocks = <&k3_clks 114 0>;
-               clock-names = "fck";
-               max-functions = /bits/ 8 <1>;
-               status = "disabled";
-       };
-
        epwm0: pwm@23000000 {
                compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
                #pwm-cells = <3>;

diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index c407f6eca343375bd2917c78deb4ec1dd361f7f1..3139f3700c8b9e7459c94431f120ac9f13a5723d 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -705,12 +705,6 @@
        num-lanes = <1>;
 };
 
-&pcie0_ep {
-       phys = <&serdes0_pcie_link>;
-       phy-names = "pcie-phy";
-       num-lanes = <1>;
-};
-
 &ecap0 {
        status = "okay";
        /* PWM is available on Pin 1 of header J12 */