phy: qcom-qmp-ufs: drop unused defines

Drop defines and enums that are unused since the QMP driver split.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20220907110728.19092-9-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 7bd3c992b841144a428e643dd5eca5bcbd1b72bb..62e9007137c93157ad0ea8d5e03e2c4163215ccf 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -28,39 +28,15 @@
 #define SW_RESET                               BIT(0)
 /* QPHY_POWER_DOWN_CONTROL */
 #define SW_PWRDN                               BIT(0)
-#define REFCLK_DRV_DSBL                                BIT(1)
 /* QPHY_START_CONTROL bits */
 #define SERDES_START                           BIT(0)
 #define PCS_START                              BIT(1)
-#define PLL_READY_GATE_EN                      BIT(3)
 /* QPHY_PCS_STATUS bit */
 #define PHYSTATUS                              BIT(6)
-#define PHYSTATUS_4_20                         BIT(7)
-/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
+/* QPHY_PCS_READY_STATUS bit */
 #define PCS_READY                              BIT(0)
 
-/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
-/* DP PHY soft reset */
-#define SW_DPPHY_RESET                         BIT(0)
-/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
-#define SW_DPPHY_RESET_MUX                     BIT(1)
-/* USB3 PHY soft reset */
-#define SW_USB3PHY_RESET                       BIT(2)
-/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
-#define SW_USB3PHY_RESET_MUX                   BIT(3)
-
-/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
-#define USB3_MODE                              BIT(0) /* enables USB3 mode */
-#define DP_MODE                                        BIT(1) /* enables DP mode */
-
-/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
-#define CLAMP_EN                               BIT(0) /* enables i/o clamp_n */
-
 #define PHY_INIT_COMPLETE_TIMEOUT              10000
-#define POWER_DOWN_DELAY_US_MIN                        10
-#define POWER_DOWN_DELAY_US_MAX                        11
-
-#define MAX_PROP_NAME                          32
 
 /* Define the assumed distance between lanes for underspecified device trees. */
 #define QMP_PHY_LEGACY_LANE_STRIDE             0x400
@@ -104,19 +80,11 @@ struct qmp_phy_init_tbl {
 
 /* set of registers with offsets different per-PHY */
 enum qphy_reg_layout {
-       /* Common block control registers */
-       QPHY_COM_SW_RESET,
-       QPHY_COM_POWER_DOWN_CONTROL,
-       QPHY_COM_START_CONTROL,
-       QPHY_COM_PCS_READY_STATUS,
        /* PCS registers */
        QPHY_SW_RESET,
        QPHY_START_CTRL,
        QPHY_PCS_READY_STATUS,
-       QPHY_PCS_STATUS,
        QPHY_PCS_POWER_DOWN_CONTROL,
-       /* PCS_MISC registers */
-       QPHY_PCS_MISC_TYPEC_CTRL,
        /* Keep last to ensure regs_layout arrays are properly initialized */
        QPHY_LAYOUT_SIZE
 };