ARM: dts: meson8b: add the DDR clock controller

Add the DDR clock controller and pass it's DDR_CLKID_DDR_PLL to the main
(HHI) clock controller as "ddr_clk". The "ddr_clk" is used as one of the
inputs for the audio clock muxes.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 1934666ff60f991010757f1adf0b86c24483be3d..8ac8bdfaf58f847c5280d47a2de1325f5ba541de 100644 (file)
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -4,6 +4,7 @@
  * Author: Carlo Caione <carlo@endlessm.com>
  */
 
+#include <dt-bindings/clock/meson8-ddr-clkc.h>
 #include <dt-bindings/clock/meson8b-clkc.h>
 #include <dt-bindings/gpio/meson8b-gpio.h>
 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
@@ -172,6 +173,14 @@
                #size-cells = <1>;
                ranges = <0x0 0xc8000000 0x8000>;
 
+               ddr_clkc: clock-controller@400 {
+                       compatible = "amlogic,meson8b-ddr-clkc";
+                       reg = <0x400 0x20>;
+                       clocks = <&xtal>;
+                       clock-names = "xtal";
+                       #clock-cells = <1>;
+               };
+
                dmcbus: bus@6000 {
                        compatible = "simple-bus";
                        reg = <0x6000 0x400>;
@@ -434,8 +443,8 @@
 &hhi {
        clkc: clock-controller {
                compatible = "amlogic,meson8-clkc";
-               clocks = <&xtal>;
-               clock-names = "xtal";
+               clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
+               clock-names = "xtal", "ddr_pll";
                #clock-cells = <1>;
                #reset-cells = <1>;
        };