drm/msm/dp: change clock related programming for YUV420 over DP

Change all relevant DP controller related programming for YUV420 cases.
Namely, change the pixel clock math to consider YUV420 and modify the
MVID programming to consider YUV420.

Changes in v2:
	- Move configuration control programming to a different commit
	- Slight code simplification
	- Add VSC SDP check when doing mode_pclk_khz division in
	  dp_bridge_mode_valid

Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/579640/
Link: https://lore.kernel.org/r/20240222194025.25329-12-quic_parellan@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c
index 541aac2cb24693db0b1c60efa6fc32bf7d93f3c7..e3c9bca01a2a164a66d2a5128eceada17384f0e6 100644 (file)
--- a/drivers/gpu/drm/msm/dp/dp_catalog.c
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
@@ -452,7 +452,7 @@ void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog,
 
 void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog,
                                        u32 rate, u32 stream_rate_khz,
-                                       bool fixed_nvid)
+                                       bool fixed_nvid, bool is_ycbcr_420)
 {
        u32 pixel_m, pixel_n;
        u32 mvid, nvid, pixel_div = 0, dispcc_input_rate;
@@ -495,6 +495,9 @@ void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog,
                nvid = temp;
        }
 
+       if (is_ycbcr_420)
+               mvid /= 2;
+
        if (link_rate_hbr2 == rate)
                nvid *= 2;
 

diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h
index a724a986b6ee12d76bf2d04db7e797ede4ec6bab..2af961e933829edbfcab3947c603fab8f2807541 100644 (file)
--- a/drivers/gpu/drm/msm/dp/dp_catalog.h
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.h
@@ -94,7 +94,7 @@ void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, bool enable);
 void dp_catalog_ctrl_psr_mainlink_enable(struct dp_catalog *dp_catalog, bool enable);
 void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, u32 cc, u32 tb);
 void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate,
-                               u32 stream_rate_khz, bool fixed_nvid);
+                               u32 stream_rate_khz, bool fixed_nvid, bool is_ycbcr_420);
 int dp_catalog_ctrl_set_pattern_state_bit(struct dp_catalog *dp_catalog, u32 pattern);
 u32 dp_catalog_hw_revision(const struct dp_catalog *dp_catalog);
 void dp_catalog_ctrl_reset(struct dp_catalog *dp_catalog);

diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index ced2ed59ca93665cf7f911142ab62ebfff11639b..f861d32d7cfafb9ddb9de2f57b999740e0d80c67 100644 (file)
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -969,7 +969,7 @@ static void dp_ctrl_calc_tu_parameters(struct dp_ctrl_private *ctrl,
        in.hporch = drm_mode->htotal - drm_mode->hdisplay;
        in.nlanes = ctrl->link->link_params.num_lanes;
        in.bpp = ctrl->panel->dp_mode.bpp;
-       in.pixel_enc = 444;
+       in.pixel_enc = ctrl->panel->dp_mode.out_fmt_is_yuv_420 ? 420 : 444;
        in.dsc_en = 0;
        in.async_en = 0;
        in.fec_en = 0;
@@ -1852,6 +1852,8 @@ int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl)
                ctrl->link->link_params.rate = rate;
                ctrl->link->link_params.num_lanes =
                        ctrl->panel->link_info.num_lanes;
+               if (ctrl->panel->dp_mode.out_fmt_is_yuv_420)
+                       pixel_rate >>= 1;
        }
 
        drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n",
@@ -1967,7 +1969,7 @@ int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train)
 
        pixel_rate = pixel_rate_orig = ctrl->panel->dp_mode.drm_mode.clock;
 
-       if (dp_ctrl->wide_bus_en)
+       if (dp_ctrl->wide_bus_en || ctrl->panel->dp_mode.out_fmt_is_yuv_420)
                pixel_rate >>= 1;
 
        drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n",
@@ -2019,7 +2021,8 @@ int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train)
 
        dp_catalog_ctrl_config_msa(ctrl->catalog,
                ctrl->link->link_params.rate,
-               pixel_rate_orig, dp_ctrl_use_fixed_nvid(ctrl));
+               pixel_rate_orig, dp_ctrl_use_fixed_nvid(ctrl),
+               ctrl->panel->dp_mode.out_fmt_is_yuv_420);
 
        dp_ctrl_setup_tr_unit(ctrl);
 

diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c
index 3960c5fb7b61f8176b5cd777bbeb99dba598cb4a..e15b4aebe2b64dc19d8c1912af4f0fc15a784bcc 100644 (file)
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -915,6 +915,10 @@ enum drm_mode_status dp_bridge_mode_valid(struct drm_bridge *bridge,
        dp_display = container_of(dp, struct dp_display_private, dp_display);
        link_info = &dp_display->panel->link_info;
 
+       if (drm_mode_is_420_only(&dp->connector->display_info, mode) &&
+           dp_display->panel->vsc_sdp_supported)
+               mode_pclk_khz /= 2;
+
        mode_bpp = dp->connector->display_info.bpc * num_components;
        if (!mode_bpp)
                mode_bpp = default_bpp;