arm64: errata: Mitigate Ampere1 erratum AC03_CPU_38 at stage-2

AmpereOne has an erratum in its implementation of FEAT_HAFDBS that
required disabling the feature on the design. This was done by reporting
the feature as not implemented in the ID register, although the
corresponding control bits were not actually RES0. This does not align
well with the requirements of the architecture, which mandates these
bits be RES0 if HAFDBS isn't implemented.

The kernel's use of stage-1 is unaffected, as the HA and HD bits are
only set if HAFDBS is detected in the ID register. KVM, on the other
hand, relies on the RES0 behavior at stage-2 to use the same value for
VTCR_EL2 on any cpu in the system. Mitigate the non-RES0 behavior by
leaving VTCR_EL2.HA clear on affected systems.

Cc: stable@vger.kernel.org
Cc: D Scott Phillips <scott@os.amperecomputing.com>
Cc: Darren Hart <darren@os.amperecomputing.com>
Acked-by: D Scott Phillips <scott@os.amperecomputing.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20230609220104.1836988-2-oliver.upton@linux.dev
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>

diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
index 9e311bc43e05eaac3c36ffb50edb6750a14a6bbe..cd46e2b20a8145117ab349f1daa5ae93047623a1 100644 (file)
--- a/Documentation/arm64/silicon-errata.rst
+++ b/Documentation/arm64/silicon-errata.rst
@@ -52,6 +52,9 @@ stable kernels.
 | Allwinner      | A64/R18         | UNKNOWN1        | SUN50I_ERRATUM_UNKNOWN1     |
 +----------------+-----------------+-----------------+-----------------------------+
 +----------------+-----------------+-----------------+-----------------------------+
+| Ampere         | AmpereOne       | AC03_CPU_38     | AMPERE_ERRATUM_AC03_CPU_38  |
++----------------+-----------------+-----------------+-----------------------------+
++----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Cortex-A510     | #2457168        | ARM64_ERRATUM_2457168       |
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Cortex-A510     | #2064142        | ARM64_ERRATUM_2064142       |

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index b1201d25a8a4ee75e6eeaddb46f626655883e6bf..0987c637fbf28b200e1884c78ed0f3e28dbc0a4b 100644 (file)
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -406,6 +406,25 @@ menu "Kernel Features"
 
 menu "ARM errata workarounds via the alternatives framework"
 
+config AMPERE_ERRATUM_AC03_CPU_38
+        bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics"
+       default y
+       help
+         This option adds an alternative code sequence to work around Ampere
+         erratum AC03_CPU_38 on AmpereOne.
+
+         The affected design reports FEAT_HAFDBS as not implemented in
+         ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0
+         as required by the architecture. The unadvertised HAFDBS
+         implementation suffers from an additional erratum where hardware
+         A/D updates can occur after a PTE has been marked invalid.
+
+         The workaround forces KVM to explicitly set VTCR_EL2.HA to 0,
+         which avoids enabling unadvertised hardware Access Flag management
+         at stage-2.
+
+         If unsure, say Y.
+
 config ARM64_WORKAROUND_CLEAN_CACHE
        bool
 

diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 307faa2b4395ed9fcacdbf9f992111cd376dc601..be66e94a21bda37ff271ea7cd8204019f74b08aa 100644 (file)
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -729,6 +729,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
                MIDR_FIXED(MIDR_CPU_VAR_REV(1,1), BIT(25)),
                .cpu_enable = cpu_clear_bf16_from_user_emulation,
        },
+#endif
+#ifdef CONFIG_AMPERE_ERRATUM_AC03_CPU_38
+       {
+               .desc = "AmpereOne erratum AC03_CPU_38",
+               .capability = ARM64_WORKAROUND_AMPERE_AC03_CPU_38,
+               ERRATA_MIDR_ALL_VERSIONS(MIDR_AMPERE1),
+       },
 #endif
        {
        }

diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c
index 5282cb9ca4cff44c638aa87b8382e011bb9e70c5..32d92ce4bae5bf4fbd2be565ec1d39587ce55317 100644 (file)
--- a/arch/arm64/kvm/hyp/pgtable.c
+++ b/arch/arm64/kvm/hyp/pgtable.c
@@ -611,10 +611,18 @@ u64 kvm_get_vtcr(u64 mmfr0, u64 mmfr1, u32 phys_shift)
 #ifdef CONFIG_ARM64_HW_AFDBM
        /*
         * Enable the Hardware Access Flag management, unconditionally
-        * on all CPUs. The features is RES0 on CPUs without the support
-        * and must be ignored by the CPUs.
+        * on all CPUs. In systems that have asymmetric support for the feature
+        * this allows KVM to leverage hardware support on the subset of cores
+        * that implement the feature.
+        *
+        * The architecture requires VTCR_EL2.HA to be RES0 (thus ignored by
+        * hardware) on implementations that do not advertise support for the
+        * feature. As such, setting HA unconditionally is safe, unless you
+        * happen to be running on a design that has unadvertised support for
+        * HAFDBS. Here be dragons.
         */
-       vtcr |= VTCR_EL2_HA;
+       if (!cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_CPU_38))
+               vtcr |= VTCR_EL2_HA;
 #endif /* CONFIG_ARM64_HW_AFDBM */
 
        /* Set the vmid bits */

diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
index 40ba95472594db7f053ec19b0d10af5088991e95..9f9a2d6652ebd424266bdfc08f798c171a985c12 100644 (file)
--- a/arch/arm64/tools/cpucaps
+++ b/arch/arm64/tools/cpucaps
@@ -77,6 +77,7 @@ WORKAROUND_2077057
 WORKAROUND_2457168
 WORKAROUND_2645198
 WORKAROUND_2658417
+WORKAROUND_AMPERE_AC03_CPU_38
 WORKAROUND_TRBE_OVERWRITE_FILL_MODE
 WORKAROUND_TSB_FLUSH_FAILURE
 WORKAROUND_TRBE_WRITE_OUT_OF_RANGE