#define XDMA_SGDMA_DESC_ADJ    0x4088
 #define XDMA_SGDMA_DESC_CREDIT 0x408c
 
-/* bits of the SG DMA control register */
-#define XDMA_CTRL_RUN_STOP                     BIT(0)
-#define XDMA_CTRL_IE_DESC_STOPPED              BIT(1)
-#define XDMA_CTRL_IE_DESC_COMPLETED            BIT(2)
-#define XDMA_CTRL_IE_DESC_ALIGN_MISMATCH       BIT(3)
-#define XDMA_CTRL_IE_MAGIC_STOPPED             BIT(4)
-#define XDMA_CTRL_IE_IDLE_STOPPED              BIT(6)
-#define XDMA_CTRL_IE_READ_ERROR                        GENMASK(13, 9)
-#define XDMA_CTRL_IE_DESC_ERROR                        GENMASK(23, 19)
-#define XDMA_CTRL_NON_INCR_ADDR                        BIT(25)
-#define XDMA_CTRL_POLL_MODE_WB                 BIT(26)
-
 /*
  * interrupt registers
  */
 
  * @vdesc: Virtual DMA descriptor
  * @chan: DMA channel pointer
  * @dir: Transferring direction of the request
- * @dev_addr: Physical address on DMA device side
  * @desc_blocks: Hardware descriptor blocks
  * @dblk_num: Number of hardware descriptor blocks
  * @desc_num: Number of hardware descriptors
        struct virt_dma_desc            vdesc;
        struct xdma_chan                *chan;
        enum dma_transfer_direction     dir;
-       u64                             dev_addr;
        struct xdma_desc_block          *desc_blocks;
        u32                             dblk_num;
        u32                             desc_num;