EDAC/amd64: Remove scrub rate control for Family 17h and later

The scrub registers on AMD Family 17h and later may be inaccessible to
the OS. Furthermore, hardware designers recommend that the scrubbing
feature is managed by the firmware.

Remove support for the sdram_scrub_rate interface for AMD Family 17h
systems and later by not setting the scrub function pointers. The EDAC MC
core will then not expose the scrub files in sysfs.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20230127170419.1824692-3-yazen.ghannam@amd.com

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 2cc7336a5121c63f1864be6dd016c842b1b9022b..07a89df0d4f4b98a2682c89ac2539003d24f2b55 100644 (file)
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -182,21 +182,6 @@ static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct,
  * other archs, we might not have access to the caches directly.
  */
 
-static inline void __f17h_set_scrubval(struct amd64_pvt *pvt, u32 scrubval)
-{
-       /*
-        * Fam17h supports scrub values between 0x5 and 0x14. Also, the values
-        * are shifted down by 0x5, so scrubval 0x5 is written to the register
-        * as 0x0, scrubval 0x6 as 0x1, etc.
-        */
-       if (scrubval >= 0x5 && scrubval <= 0x14) {
-               scrubval -= 0x5;
-               pci_write_bits32(pvt->F6, F17H_SCR_LIMIT_ADDR, scrubval, 0xF);
-               pci_write_bits32(pvt->F6, F17H_SCR_BASE_ADDR, 1, 0x1);
-       } else {
-               pci_write_bits32(pvt->F6, F17H_SCR_BASE_ADDR, 0, 0x1);
-       }
-}
 /*
  * Scan the scrub rate mapping table for a close or matching bandwidth value to
  * issue. If requested is too big, then use last maximum value found.
@@ -229,9 +214,7 @@ static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate)
 
        scrubval = scrubrates[i].scrubval;
 
-       if (pvt->umc) {
-               __f17h_set_scrubval(pvt, scrubval);
-       } else if (pvt->fam == 0x15 && pvt->model == 0x60) {
+       if (pvt->fam == 0x15 && pvt->model == 0x60) {
                f15h_select_dct(pvt, 0);
                pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F);
                f15h_select_dct(pvt, 1);
@@ -271,16 +254,7 @@ static int get_scrub_rate(struct mem_ctl_info *mci)
        int i, retval = -EINVAL;
        u32 scrubval = 0;
 
-       if (pvt->umc) {
-               amd64_read_pci_cfg(pvt->F6, F17H_SCR_BASE_ADDR, &scrubval);
-               if (scrubval & BIT(0)) {
-                       amd64_read_pci_cfg(pvt->F6, F17H_SCR_LIMIT_ADDR, &scrubval);
-                       scrubval &= 0xF;
-                       scrubval += 0x5;
-               } else {
-                       scrubval = 0;
-               }
-       } else if (pvt->fam == 0x15) {
+       if (pvt->fam == 0x15) {
                /* Erratum #505 */
                if (pvt->model < 0x10)
                        f15h_select_dct(pvt, 0);
@@ -3967,6 +3941,9 @@ static void setup_mci_misc_attrs(struct mem_ctl_info *mci)
        mci->dev_name           = pci_name(pvt->F3);
        mci->ctl_page_to_phys   = NULL;
 
+       if (pvt->fam >= 0x17)
+               return;
+
        /* memory scrubber interface */
        mci->set_sdram_scrub_rate = set_scrub_rate;
        mci->get_sdram_scrub_rate = get_scrub_rate;

diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 38e5ad95d01097f7940712585f6fbf86bda5d5b6..48f1d97e12743b43803b472d885b0e043469abc9 100644 (file)
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -215,8 +215,6 @@
 #define DCT_SEL_HI                     0x114
 
 #define F15H_M60H_SCRCTRL              0x1C8
-#define F17H_SCR_BASE_ADDR             0x48
-#define F17H_SCR_LIMIT_ADDR            0x4C
 
 /*
  * Function 3 - Misc Control