arm64: dts: qcom: sm8550: Mark DWC3 as dma-coherent

In a fairly new development, Qualcomm somehow made the DWC3 block
cache-coherent. Annotate that.

Fixes: 7f7e5c1b037f ("arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240210-topic-1v-v1-6-fda0db38e29b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index a72627f4d8cd0c8b25fa7a0ee8d063e246df033e..5adb9b178b05a577ae929fb47ef2f2b2e30b8ef2 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -3245,6 +3245,7 @@
                                snps,usb2-lpm-disable;
                                snps,has-lpm-erratum;
                                tx-fifo-resize;
+                               dma-coherent;
 
                                ports {
                                        #address-cells = <1>;