Add the uSDHC node for the boards that are based on S32G SoCs.
Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Chester Lin <chester62515@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
                        status = "disabled";
                };
 
+               usdhc0: mmc@402f0000 {
+                       compatible = "nxp,s32g2-usdhc";
+                       reg = <0x402f0000 0x1000>;
+                       interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks 32>, <&clks 31>, <&clks 33>;
+                       clock-names = "ipg", "ahb", "per";
+                       bus-width = <8>;
+                       status = "disabled";
+               };
+
                gic: interrupt-controller@50800000 {
                        compatible = "arm,gic-v3";
                        reg = <0x50800000 0x10000>,
 
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
  * Copyright (c) 2021 SUSE LLC
- * Copyright (c) 2019-2021 NXP
+ * Copyright 2019-2021, 2024 NXP
  */
 
 /dts-v1/;
 &uart0 {
        status = "okay";
 };
+
+&usdhc0 {
+       status = "okay";
+};
 
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
  * Copyright (c) 2021 SUSE LLC
- * Copyright (c) 2019-2021 NXP
+ * Copyright 2019-2021, 2024 NXP
  */
 
 /dts-v1/;
 &uart1 {
        status = "okay";
 };
+
+&usdhc0 {
+       status = "okay";
+};