arm64: dts: s32g: add uSDHC node
authorGhennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Mon, 22 Jan 2024 14:06:01 +0000 (16:06 +0200)
committerShawn Guo <shawnguo@kernel.org>
Thu, 28 Mar 2024 06:37:23 +0000 (14:37 +0800)
Add the uSDHC node for the boards that are based on S32G SoCs.

Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Chester Lin <chester62515@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm64/boot/dts/freescale/s32g2.dtsi
arch/arm64/boot/dts/freescale/s32g274a-evb.dts
arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts

index ef1a1d61f2ba6d7f0dab0b8c342527bfd4d3a63e..fc19ae2e8d3bc4b2e40bc34bcbe402782f4e77ca 100644 (file)
                        status = "disabled";
                };
 
+               usdhc0: mmc@402f0000 {
+                       compatible = "nxp,s32g2-usdhc";
+                       reg = <0x402f0000 0x1000>;
+                       interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks 32>, <&clks 31>, <&clks 33>;
+                       clock-names = "ipg", "ahb", "per";
+                       bus-width = <8>;
+                       status = "disabled";
+               };
+
                gic: interrupt-controller@50800000 {
                        compatible = "arm,gic-v3";
                        reg = <0x50800000 0x10000>,
index 9118d8d2ee019babf2cf45c5c80710f7bba0037a..00070c949e2ab2b97ae310ecf660776a0a824cf9 100644 (file)
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
  * Copyright (c) 2021 SUSE LLC
- * Copyright (c) 2019-2021 NXP
+ * Copyright 2019-2021, 2024 NXP
  */
 
 /dts-v1/;
@@ -32,3 +32,7 @@
 &uart0 {
        status = "okay";
 };
+
+&usdhc0 {
+       status = "okay";
+};
index e05ee854cdf5e39854a41ffd8677cdda9b58c7be..b3fc12899cae52971da507f4a71e5fe33116210a 100644 (file)
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
  * Copyright (c) 2021 SUSE LLC
- * Copyright (c) 2019-2021 NXP
+ * Copyright 2019-2021, 2024 NXP
  */
 
 /dts-v1/;
@@ -38,3 +38,7 @@
 &uart1 {
        status = "okay";
 };
+
+&usdhc0 {
+       status = "okay";
+};