#define SVM_NPT_NXE (1 << 2)
#define SVM_NPT_PSE (1 << 3)
-#define SVM_NPTEXIT_P (1ULL << 0)
-#define SVM_NPTEXIT_RW (1ULL << 1)
-#define SVM_NPTEXIT_US (1ULL << 2)
-#define SVM_NPTEXIT_RSVD (1ULL << 3)
-#define SVM_NPTEXIT_ID (1ULL << 4)
#define SVM_NPTEXIT_GPA (1ULL << 32)
#define SVM_NPTEXIT_GPT (1ULL << 33)
return pte + page_offset;
do_fault_rsvd:
- exit_info_1 |= SVM_NPTEXIT_RSVD;
+ exit_info_1 |= PG_ERROR_RSVD_MASK;
do_fault_protect:
- exit_info_1 |= SVM_NPTEXIT_P;
+ exit_info_1 |= PG_ERROR_P_MASK;
do_fault:
x86_stq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
gphys);
- exit_info_1 |= SVM_NPTEXIT_US;
+ exit_info_1 |= PG_ERROR_U_MASK;
if (access_type == MMU_DATA_STORE) {
- exit_info_1 |= SVM_NPTEXIT_RW;
+ exit_info_1 |= PG_ERROR_W_MASK;
} else if (access_type == MMU_INST_FETCH) {
- exit_info_1 |= SVM_NPTEXIT_ID;
+ exit_info_1 |= PG_ERROR_I_D_MASK;
}
if (prot) {
exit_info_1 |= SVM_NPTEXIT_GPA;