drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB
authorVandita Kulkarni <vandita.kulkarni@intel.com>
Tue, 19 Oct 2021 15:14:32 +0000 (20:44 +0530)
committerVandita Kulkarni <vandita.kulkarni@intel.com>
Mon, 15 Nov 2021 05:45:04 +0000 (11:15 +0530)
v2: Fix the typo, move out the hardcoding from
    macro(Jani, Ville)

Fixes: f87c46c43175 ("drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband")
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211019151435.20477-2-vandita.kulkarni@intel.com
drivers/gpu/drm/i915/display/icl_dsi.c
drivers/gpu/drm/i915/i915_reg.h

index c05fb861f10c644a69ed9dcf63003e514d7d5b64..edc38fbd2545de95c47fedb720b009fae7541ebe 100644 (file)
@@ -1269,7 +1269,8 @@ static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
        if (DISPLAY_VER(i915) == 13) {
                for_each_dsi_port(port, intel_dsi->ports)
                        intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
-                                    TGL_DSI_CHKN_LSHS_GB, 0x4);
+                                    TGL_DSI_CHKN_LSHS_GB_MASK,
+                                    TGL_DSI_CHKN_LSHS_GB(4));
        }
 }
 
index 7d182d2ca7e69e82eefe824a0489b86e0e9be0a3..a6dcf252a70fc92942d5c65faf006bb0c943486c 100644 (file)
@@ -11730,7 +11730,9 @@ enum skl_power_gate {
 #define TGL_DSI_CHKN_REG(port)         _MMIO_PORT(port,        \
                                                    _TGL_DSI_CHKN_REG_0, \
                                                    _TGL_DSI_CHKN_REG_1)
-#define TGL_DSI_CHKN_LSHS_GB                   REG_GENMASK(15, 12)
+#define TGL_DSI_CHKN_LSHS_GB_MASK              REG_GENMASK(15, 12)
+#define TGL_DSI_CHKN_LSHS_GB(byte_clocks)      REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, \
+                                                              (byte_clocks))
 
 /* Display Stream Splitter Control */
 #define DSS_CTL1                               _MMIO(0x67400)