arm64: dts: imx8mn: Slow default video_pll clock rate

Since commit 8208181fe536 ("clk: imx: composite-8m:
Add imx8m_divider_determine_rate") the lcdif controller has
had the ability to set the disp_pixel_clk rate which propagates
up the tree and sets the video_pll rate automatically.

By setting this value low, it will force the recalculation of
video_pll to the lowest rate needed by lcdif instead of
dividing a larger clock down to the desired clock speed. This
has the  advantage of being able to lower the video_pll rate
from 594MHz to 148.5MHz when operating at 1080p. It can go even
lower when operating at lower resolutions and refresh rates.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 136e75c51251a60c7a7f831d7e987ea27241f6a4..932c8b05c75fc06ea394bcdc0f8fbe049dade17d 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -1168,7 +1168,7 @@
                                                         <&clk IMX8MN_SYS_PLL1_800M>;
                                assigned-clock-rates = <266000000>,
                                                       <24000000>,
-                                                      <594000000>,
+                                                      <24000000>,
                                                       <500000000>,
                                                       <200000000>;
                                #power-domain-cells = <1>;