arm64: dts: qcom: sdm630: Add DMA to I2C hosts
authorKonrad Dybcio <konrad.dybcio@somainline.org>
Wed, 28 Jul 2021 22:25:42 +0000 (00:25 +0200)
committerBjorn Andersson <bjorn.andersson@linaro.org>
Wed, 4 Aug 2021 20:07:05 +0000 (15:07 -0500)
Add DMA properties to I2C hosts to allow for DMA transfers.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210728222542.54269-40-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
arch/arm64/boot/dts/qcom/sdm630.dtsi

index 557f81d94130db2e9c4c533aa5667dcf7859177a..c77d4e4305d62bea0d74b8252d0d49abf40d68b4 100644 (file)
                                        <&gcc GCC_BLSP1_AHB_CLK>;
                        clock-names = "core", "iface";
                        clock-frequency = <400000>;
+                       dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
+                       dma-names = "tx", "rx";
 
                        pinctrl-names = "default", "sleep";
                        pinctrl-0 = <&i2c1_default>;
                                 <&gcc GCC_BLSP1_AHB_CLK>;
                        clock-names = "core", "iface";
                        clock-frequency = <400000>;
+                       dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
+                       dma-names = "tx", "rx";
 
                        pinctrl-names = "default", "sleep";
                        pinctrl-0 = <&i2c2_default>;
                                 <&gcc GCC_BLSP1_AHB_CLK>;
                        clock-names = "core", "iface";
                        clock-frequency = <400000>;
+                       dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
+                       dma-names = "tx", "rx";
 
                        pinctrl-names = "default", "sleep";
                        pinctrl-0 = <&i2c3_default>;
                                 <&gcc GCC_BLSP1_AHB_CLK>;
                        clock-names = "core", "iface";
                        clock-frequency = <400000>;
+                       dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
+                       dma-names = "tx", "rx";
 
                        pinctrl-names = "default", "sleep";
                        pinctrl-0 = <&i2c4_default>;
                                 <&gcc GCC_BLSP2_AHB_CLK>;
                        clock-names = "core", "iface";
                        clock-frequency = <400000>;
+                       dmas = <&blsp2_dma 4>, <&blsp2_dma 5>;
+                       dma-names = "tx", "rx";
 
                        pinctrl-names = "default", "sleep";
                        pinctrl-0 = <&i2c5_default>;
                                 <&gcc GCC_BLSP2_AHB_CLK>;
                        clock-names = "core", "iface";
                        clock-frequency = <400000>;
+                       dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
+                       dma-names = "tx", "rx";
 
                        pinctrl-names = "default", "sleep";
                        pinctrl-0 = <&i2c6_default>;
                                 <&gcc GCC_BLSP2_AHB_CLK>;
                        clock-names = "core", "iface";
                        clock-frequency = <400000>;
+                       dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
+                       dma-names = "tx", "rx";
 
                        pinctrl-names = "default", "sleep";
                        pinctrl-0 = <&i2c7_default>;
                                 <&gcc GCC_BLSP2_AHB_CLK>;
                        clock-names = "core", "iface";
                        clock-frequency = <400000>;
+                       dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
+                       dma-names = "tx", "rx";
 
                        pinctrl-names = "default", "sleep";
                        pinctrl-0 = <&i2c8_default>;