drm/xe: Update definition of GT_INTR_DW

Add bits definitions that we will be using in upcoming patch.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231214185955.1791-5-michal.wajdeczko@intel.com
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 1dd361046b5dc028c8f68b0fd4c52a71c482a68d..6aaaf1f63c728abf083bdb81af03f802321c3190 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -430,6 +430,15 @@
 #define   VOLTAGE_MASK                         REG_GENMASK(10, 0)
 
 #define GT_INTR_DW(x)                          XE_REG(0x190018 + ((x) * 4))
+#define   INTR_GSC                             REG_BIT(31)
+#define   INTR_GUC                             REG_BIT(25)
+#define   INTR_MGUC                            REG_BIT(24)
+#define   INTR_BCS8                            REG_BIT(23)
+#define   INTR_BCS(x)                          REG_BIT(15 - (x))
+#define   INTR_CCS(x)                          REG_BIT(4 + (x))
+#define   INTR_RCS0                            REG_BIT(0)
+#define   INTR_VECS(x)                         REG_BIT(31 - (x))
+#define   INTR_VCS(x)                          REG_BIT(x)
 
 #define RENDER_COPY_INTR_ENABLE                        XE_REG(0x190030)
 #define VCS_VECS_INTR_ENABLE                   XE_REG(0x190034)