hwrng: mpfs - add polarfire soc hwrng support

Add a driver to access the hardware random number generator on the
Polarfire SoC. The hwrng can only be accessed via the system controller,
so use the mailbox interface the system controller exposes to access the
hwrng.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index a087156a58186ab13f0f8491b23e4b504e48b76d..c3a9f17bf31ce29f71be4b05766a0269d6b6a7af 100644 (file)
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -385,6 +385,19 @@ config HW_RANDOM_PIC32
 
          If unsure, say Y.
 
+config HW_RANDOM_POLARFIRE_SOC
+       tristate "Microchip PolarFire SoC Random Number Generator support"
+       depends on HW_RANDOM && POLARFIRE_SOC_SYS_CTRL
+       help
+         This driver provides kernel-side support for the Random Number
+         Generator hardware found on PolarFire SoC (MPFS).
+
+         To compile this driver as a module, choose M here. The
+         module will be called mfps_rng.
+
+         If unsure, say N.
+
+
 config HW_RANDOM_MESON
        tristate "Amlogic Meson Random Number Generator support"
        depends on HW_RANDOM

diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
index 584d47ba32f7677b4e56229588837b1f0597d840..3e948cf044762cd4fd6b5ca94cb6a4ff9940cae4 100644 (file)
--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
@@ -46,3 +46,4 @@ obj-$(CONFIG_HW_RANDOM_CCTRNG) += cctrng.o
 obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphera-trng.o
 obj-$(CONFIG_HW_RANDOM_ARM_SMCCC_TRNG) += arm_smccc_trng.o
 obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o
+obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) += mpfs-rng.o

diff --git a/drivers/char/hw_random/mpfs-rng.c b/drivers/char/hw_random/mpfs-rng.c
new file mode 100644 (file)
index 0000000..5813da6
--- /dev/null
+++ b/drivers/char/hw_random/mpfs-rng.c
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Microchip PolarFire SoC (MPFS) hardware random driver
+ *
+ * Copyright (c) 2020-2022 Microchip Corporation. All rights reserved.
+ *
+ * Author: Conor Dooley <conor.dooley@microchip.com>
+ */
+
+#include <linux/module.h>
+#include <linux/hw_random.h>
+#include <linux/platform_device.h>
+#include <soc/microchip/mpfs.h>
+
+#define CMD_OPCODE     0x21
+#define CMD_DATA_SIZE  0U
+#define CMD_DATA       NULL
+#define MBOX_OFFSET    0U
+#define RESP_OFFSET    0U
+#define RNG_RESP_BYTES 32U
+
+struct mpfs_rng {
+       struct mpfs_sys_controller *sys_controller;
+       struct hwrng rng;
+};
+
+static int mpfs_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+{
+       struct mpfs_rng *rng_priv = container_of(rng, struct mpfs_rng, rng);
+       u32 response_msg[RNG_RESP_BYTES / sizeof(u32)];
+       unsigned int count = 0, copy_size_bytes;
+       int ret;
+
+       struct mpfs_mss_response response = {
+               .resp_status = 0U,
+               .resp_msg = (u32 *)response_msg,
+               .resp_size = RNG_RESP_BYTES
+       };
+       struct mpfs_mss_msg msg = {
+               .cmd_opcode = CMD_OPCODE,
+               .cmd_data_size = CMD_DATA_SIZE,
+               .response = &response,
+               .cmd_data = CMD_DATA,
+               .mbox_offset = MBOX_OFFSET,
+               .resp_offset = RESP_OFFSET
+       };
+
+       while (count < max) {
+               ret = mpfs_blocking_transaction(rng_priv->sys_controller, &msg);
+               if (ret)
+                       return ret;
+
+               copy_size_bytes = max - count > RNG_RESP_BYTES ? RNG_RESP_BYTES : max - count;
+               memcpy(buf + count, response_msg, copy_size_bytes);
+
+               count += copy_size_bytes;
+               if (!wait)
+                       break;
+       }
+
+       return count;
+}
+
+static int mpfs_rng_probe(struct platform_device *pdev)
+{
+       struct device *dev = &pdev->dev;
+       struct mpfs_rng *rng_priv;
+       int ret;
+
+       rng_priv = devm_kzalloc(dev, sizeof(*rng_priv), GFP_KERNEL);
+       if (!rng_priv)
+               return -ENOMEM;
+
+       rng_priv->sys_controller =  mpfs_sys_controller_get(&pdev->dev);
+       if (IS_ERR(rng_priv->sys_controller))
+               return dev_err_probe(dev, PTR_ERR(rng_priv->sys_controller),
+                                    "Failed to register system controller hwrng sub device\n");
+
+       rng_priv->rng.read = mpfs_rng_read;
+       rng_priv->rng.name = pdev->name;
+       rng_priv->rng.quality = 1024;
+
+       platform_set_drvdata(pdev, rng_priv);
+
+       ret = devm_hwrng_register(&pdev->dev, &rng_priv->rng);
+       if (ret)
+               return dev_err_probe(&pdev->dev, ret, "Failed to register MPFS hwrng\n");
+
+       dev_info(&pdev->dev, "Registered MPFS hwrng\n");
+
+       return 0;
+}
+
+static struct platform_driver mpfs_rng_driver = {
+       .driver = {
+               .name = "mpfs-rng",
+       },
+       .probe = mpfs_rng_probe,
+};
+module_platform_driver(mpfs_rng_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
+MODULE_DESCRIPTION("PolarFire SoC (MPFS) hardware random driver");