arm64: dts: qcom: msm8996: Add PCIe bridge node

On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-14-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 1601e46549e77990dafbd63894b9c078ffec60af..8d2cb6f410956e84fe58eba0bc384289651c4f2a 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1929,6 +1929,16 @@
                                                "cfg",
                                                "bus_master",
                                                "bus_slave";
+
+                               pcie@0 {
+                                       device_type = "pci";
+                                       reg = <0x0 0x0 0x0 0x0 0x0>;
+                                       bus-range = <0x01 0xff>;
+
+                                       #address-cells = <3>;
+                                       #size-cells = <2>;
+                                       ranges;
+                               };
                        };
 
                        pcie1: pcie@608000 {
@@ -1982,6 +1992,16 @@
                                                "cfg",
                                                "bus_master",
                                                "bus_slave";
+
+                               pcie@0 {
+                                       device_type = "pci";
+                                       reg = <0x0 0x0 0x0 0x0 0x0>;
+                                       bus-range = <0x01 0xff>;
+
+                                       #address-cells = <3>;
+                                       #size-cells = <2>;
+                                       ranges;
+                               };
                        };
 
                        pcie2: pcie@610000 {
@@ -2032,6 +2052,16 @@
                                                "cfg",
                                                "bus_master",
                                                "bus_slave";
+
+                               pcie@0 {
+                                       device_type = "pci";
+                                       reg = <0x0 0x0 0x0 0x0 0x0>;
+                                       bus-range = <0x01 0xff>;
+
+                                       #address-cells = <3>;
+                                       #size-cells = <2>;
+                                       ranges;
+                               };
                        };
                };