drm/i915: Sipmplify PLANE_STRIDE masking

There's no need to have separate masks for the stride bitfield
in PLANE_STRIDE for different platforms. All the extra bits
are hardcoded to zero anyway.

Also the masks we're using now don't even match the actual hardware
since the bitfield was only 10 bits on skl/derivatives, only getting
bumped to 11 bits on glk.

So let's just use a 12 bit mask for everything.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211201152552.7821-5-ville.syrjala@linux.intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 158d89b8d490e7c50c2666c6e58c0400dfa97793..ec115505aac25d5f12e250503df757b214b3b307 100644 (file)
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2374,10 +2374,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
        val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
        stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
 
-       if (DISPLAY_VER(dev_priv) >= 13)
-               fb->pitches[0] = (val & PLANE_STRIDE_MASK_XELPD) * stride_mult;
-       else
-               fb->pitches[0] = (val & PLANE_STRIDE_MASK) * stride_mult;
+       fb->pitches[0] = (val & PLANE_STRIDE_MASK) * stride_mult;
 
        aligned_height = intel_fb_align_height(fb, 0, fb->height);
 

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4424807c8decaed81c32f2fb9883a9b330113360..f13d5886b6bd7ab175fd5fa30d116f1f23b64cfa 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6435,8 +6435,7 @@ enum {
        _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
 #define PLANE_STRIDE(pipe, plane)      \
        _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
-#define PLANE_STRIDE_MASK              REG_GENMASK(10, 0)
-#define PLANE_STRIDE_MASK_XELPD                REG_GENMASK(11, 0)
+#define PLANE_STRIDE_MASK              REG_GENMASK(11, 0)
 
 #define _PLANE_POS_1_B                         0x7118c
 #define _PLANE_POS_2_B                         0x7128c