scsi: ufs: core: mcq: Calculate queue depth

The UFS device defines the supported queuedepth by bqueuedepth which has a
max value of 256.  The HC defines MAC (Max Active Commands) that defines
the max number of commands that in flight to the UFS device.  Calculate and
configure the nutrs based on both these values.

Co-developed-by: Can Guo <quic_cang@quicinc.com>
Signed-off-by: Can Guo <quic_cang@quicinc.com>
Signed-off-by: Asutosh Das <quic_asutoshd@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Bart Van Assche <bvanassche@acm.org>
Reviewed-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>

diff --git a/drivers/ufs/core/ufs-mcq.c b/drivers/ufs/core/ufs-mcq.c
index 65c00373af0e7203459f0d87252fe1c8feda11bc..2f680ff5cafca4071fee1f8d682f5e017f7679e1 100644 (file)
--- a/drivers/ufs/core/ufs-mcq.c
+++ b/drivers/ufs/core/ufs-mcq.c
@@ -19,6 +19,9 @@
 #define UFS_MCQ_NUM_DEV_CMD_QUEUES 1
 #define UFS_MCQ_MIN_POLL_QUEUES 0
 
+#define MAX_DEV_CMD_ENTRIES    2
+#define MCQ_CFG_MAC_MASK       GENMASK(16, 8)
+
 static int rw_queue_count_set(const char *val, const struct kernel_param *kp)
 {
        return param_set_uint_minmax(val, kp, UFS_MCQ_MIN_RW_QUEUES,
@@ -67,6 +70,38 @@ module_param_cb(poll_queues, &poll_queue_count_ops, &poll_queues, 0644);
 MODULE_PARM_DESC(poll_queues,
                 "Number of poll queues used for r/w. Default value is 1");
 
+/**
+ * ufshcd_mcq_decide_queue_depth - decide the queue depth
+ * @hba - per adapter instance
+ *
+ * Returns queue-depth on success, non-zero on error
+ *
+ * MAC - Max. Active Command of the Host Controller (HC)
+ * HC wouldn't send more than this commands to the device.
+ * It is mandatory to implement get_hba_mac() to enable MCQ mode.
+ * Calculates and adjusts the queue depth based on the depth
+ * supported by the HC and ufs device.
+ */
+int ufshcd_mcq_decide_queue_depth(struct ufs_hba *hba)
+{
+       int mac;
+
+       /* Mandatory to implement get_hba_mac() */
+       mac = ufshcd_mcq_vops_get_hba_mac(hba);
+       if (mac < 0) {
+               dev_err(hba->dev, "Failed to get mac, err=%d\n", mac);
+               return mac;
+       }
+
+       WARN_ON_ONCE(!hba->dev_info.bqueuedepth);
+       /*
+        * max. value of bqueuedepth = 256, mac is host dependent.
+        * It is mandatory for UFS device to define bQueueDepth if
+        * shared queuing architecture is enabled.
+        */
+       return min_t(int, mac, hba->dev_info.bqueuedepth);
+}
+
 static int ufshcd_mcq_config_nr_queues(struct ufs_hba *hba)
 {
        int i;

diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h
index e3bc4ce274e3dde6a7fe51a01de5c54d7c11100e..11076c3111c5e76ef7129bd87a03f44817062520 100644 (file)
--- a/drivers/ufs/core/ufshcd-priv.h
+++ b/drivers/ufs/core/ufshcd-priv.h
@@ -62,6 +62,7 @@ int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
        enum flag_idn idn, u8 index, bool *flag_res);
 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit);
 int ufshcd_mcq_init(struct ufs_hba *hba);
+int ufshcd_mcq_decide_queue_depth(struct ufs_hba *hba);
 
 #define SD_ASCII_STD true
 #define SD_RAW false
@@ -238,6 +239,14 @@ static inline int ufshcd_vops_mcq_config_resource(struct ufs_hba *hba)
        return -EOPNOTSUPP;
 }
 
+static inline int ufshcd_mcq_vops_get_hba_mac(struct ufs_hba *hba)
+{
+       if (hba->vops && hba->vops->get_hba_mac)
+               return hba->vops->get_hba_mac(hba);
+
+       return -EOPNOTSUPP;
+}
+
 extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[];
 
 /**

diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 97120867a2a0e91da0c4b5bad4cc446f658c6db7..5c8570c8e100ea563617456690a4c937dd86dd27 100644 (file)
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -7887,6 +7887,7 @@ static int ufs_get_device_desc(struct ufs_hba *hba)
        /* getting Specification Version in big endian format */
        dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 |
                                      desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1];
+       dev_info->bqueuedepth = desc_buf[DEVICE_DESC_PARAM_Q_DPTH];
        b_ufs_feature_sup = desc_buf[DEVICE_DESC_PARAM_UFS_FEAT];
 
        model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
@@ -8296,7 +8297,21 @@ out:
 
 static int ufshcd_alloc_mcq(struct ufs_hba *hba)
 {
-       return ufshcd_mcq_init(hba);
+       int ret;
+       int old_nutrs = hba->nutrs;
+
+       ret = ufshcd_mcq_decide_queue_depth(hba);
+       if (ret < 0)
+               return ret;
+
+       hba->nutrs = ret;
+       ret = ufshcd_mcq_init(hba);
+       if (ret) {
+               hba->nutrs = old_nutrs;
+               return ret;
+       }
+
+       return 0;
 }
 
 static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params)

diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 2a1434ff0501828734b66d117be2e97ff2b0a714..edd7225065df45e63c2b02a8b88403a766c01613 100644 (file)
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -1496,6 +1496,12 @@ insert_res_err:
        return ret;
 }
 
+static int ufs_qcom_get_hba_mac(struct ufs_hba *hba)
+{
+       /* Qualcomm HC supports up to 64 */
+       return MAX_SUPP_MAC;
+}
+
 /*
  * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
  *
@@ -1521,6 +1527,7 @@ static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
        .program_key            = ufs_qcom_ice_program_key,
        .reinit_notify          = ufs_qcom_reinit_notify,
        .mcq_config_resource    = ufs_qcom_mcq_config_resource,
+       .get_hba_mac            = ufs_qcom_get_hba_mac,
 };
 
 /**

diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index f744a9e6200273ec2cba162304a9d862377dc68f..164e18b6b1fb81b9681324edef1a6dc8f32474ab 100644 (file)
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -16,6 +16,7 @@
 #define HBRN8_POLL_TOUT_MS      100
 #define DEFAULT_CLK_RATE_HZ     1000000
 #define BUS_VECTOR_NAME_LEN     32
+#define MAX_SUPP_MAC           64
 
 #define UFS_HW_VER_MAJOR_MASK  GENMASK(31, 28)
 #define UFS_HW_VER_MINOR_MASK  GENMASK(27, 16)

diff --git a/include/ufs/ufs.h b/include/ufs/ufs.h
index bea7b2086a4a60a102493d5210776618858ace02..4e8d6240e589bdf1b735f7527651eb149f4ff949 100644 (file)
--- a/include/ufs/ufs.h
+++ b/include/ufs/ufs.h
@@ -617,6 +617,8 @@ struct ufs_dev_info {
        u8      *model;
        u16     wspecversion;
        u32     clk_gating_wait_us;
+       /* Stores the depth of queue in UFS device */
+       u8      bqueuedepth;
 
        /* UFS HPB related flag */
        bool    hpb_enabled;

diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h
index 81c7494cecad472d9552600e69aa90f1276020d6..57854bb0395eebac6acfc0c32dfde265e0aeb5b3 100644 (file)
--- a/include/ufs/ufshcd.h
+++ b/include/ufs/ufshcd.h
@@ -301,6 +301,7 @@ struct ufs_pwr_mode_info {
  * @event_notify: called to notify important events
  * @reinit_notify: called to notify reinit of UFSHCD during max gear switch
  * @mcq_config_resource: called to configure MCQ platform resources
+ * @get_hba_mac: called to get vendor specific mac value, mandatory for mcq mode
  */
 struct ufs_hba_variant_ops {
        const char *name;
@@ -341,6 +342,7 @@ struct ufs_hba_variant_ops {
                                enum ufs_event_type evt, void *data);
        void    (*reinit_notify)(struct ufs_hba *);
        int     (*mcq_config_resource)(struct ufs_hba *hba);
+       int     (*get_hba_mac)(struct ufs_hba *hba);
 };
 
 /* clock gating state  */

diff --git a/include/ufs/ufshci.h b/include/ufs/ufshci.h
index f41bc7b03092d2af32256e1c6916a12f624778f7..845a82a57f6557616e7080182e4423b8f4eb223e 100644 (file)
--- a/include/ufs/ufshci.h
+++ b/include/ufs/ufshci.h
@@ -57,6 +57,7 @@ enum {
        REG_UFS_CCAP                            = 0x100,
        REG_UFS_CRYPTOCAP                       = 0x104,
 
+       REG_UFS_MCQ_CFG                         = 0x380,
        UFSHCI_CRYPTO_REG_SPACE_SIZE            = 0x400,
 };