ARM: dts: Add missing omap5 secure clocks

The secure clocks on omap5 are similar to what we already have for dra7
with dra7_l4sec_clkctrl_regs and documented in the omap5432 TRM in
"Table 3-1044. CORE_CM_CORE Registers Mapping Summary".

The secure clocks are part of the l4per clock manager. As the l4per
clock manager has now two clock domains as children, let's also update
the l4per clockdomain node name to follow the "clock" node naming with
a domain specific compatible property.

Compared to omap4, omap5 has more clocks working in hardare autogating
mode.

Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
index 4791834dacb2ef1814c195a85912941d8a28123e..42f2c447727dfa045421927afc1e7b360e79867d 100644 (file)
--- a/arch/arm/boot/dts/omap54xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -1125,11 +1125,17 @@
                #size-cells = <1>;
                ranges = <0 0x1000 0x200>;
 
-               l4per_clkctrl: clk@20 {
-                       compatible = "ti,clkctrl";
+               l4per_clkctrl: clock@20 {
+                       compatible = "ti,clkctrl-l4per", "ti,clkctrl";
                        reg = <0x20 0x15c>;
                        #clock-cells = <2>;
                };
+
+               l4sec_clkctrl: clock@1a0 {
+                       compatible = "ti,clkctrl-l4sec", "ti,clkctrl";
+                       reg = <0x1a0 0x3c>;
+                       #clock-cells = <2>;
+               };
        };
 
        dss_cm: dss_cm@1400 {

diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c
index 14d98a890c02730265b33da6dc9de6725b5e2582..92bf2dda95b9b228b045cf8dc17e162f3995cef7 100644 (file)
--- a/drivers/clk/ti/clk-54xx.c
+++ b/drivers/clk/ti/clk-54xx.c
@@ -301,6 +301,18 @@ static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst
        { 0 },
 };
 
+static const struct
+omap_clkctrl_reg_data omap5_l4_secure_clkctrl_regs[] __initconst = {
+       { OMAP5_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "" },
+       { OMAP5_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "" },
+       { OMAP5_DES3DES_CLKCTRL, NULL, CLKF_HW_SUP, "" },
+       { OMAP5_FPKA_CLKCTRL, NULL, CLKF_SW_SUP, "" },
+       { OMAP5_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" },
+       { OMAP5_SHA2MD5_CLKCTRL, NULL, CLKF_HW_SUP, "" },
+       { OMAP5_DMA_CRYPTO_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" },
+       { 0 },
+};
+
 static const struct omap_clkctrl_reg_data omap5_iva_clkctrl_regs[] __initconst = {
        { OMAP5_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
        { OMAP5_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
@@ -523,6 +535,7 @@ const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
        { 0x4a008d20, omap5_l4cfg_clkctrl_regs },
        { 0x4a008e20, omap5_l3instr_clkctrl_regs },
        { 0x4a009020, omap5_l4per_clkctrl_regs },
+       { 0x4a0091a0, omap5_l4_secure_clkctrl_regs },
        { 0x4a009220, omap5_iva_clkctrl_regs },
        { 0x4a009420, omap5_dss_clkctrl_regs },
        { 0x4a009520, omap5_gpu_clkctrl_regs },

diff --git a/include/dt-bindings/clock/omap5.h b/include/dt-bindings/clock/omap5.h
index 2b4fd9a96b9193fca63d2bade278513a8e6e57f1..41775272fd2754306778da32f2a29127b8f9cef4 100644 (file)
--- a/include/dt-bindings/clock/omap5.h
+++ b/include/dt-bindings/clock/omap5.h
@@ -87,6 +87,17 @@
 #define OMAP5_UART5_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x170)
 #define OMAP5_UART6_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x178)
 
+/* l4_secure clocks */
+#define OMAP5_L4_SECURE_CLKCTRL_OFFSET 0x1a0
+#define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset)  ((offset) - OMAP5_L4_SECURE_CLKCTRL_OFFSET)
+#define OMAP5_AES1_CLKCTRL     OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a0)
+#define OMAP5_AES2_CLKCTRL     OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a8)
+#define OMAP5_DES3DES_CLKCTRL  OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b0)
+#define OMAP5_FPKA_CLKCTRL     OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b8)
+#define OMAP5_RNG_CLKCTRL      OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c0)
+#define OMAP5_SHA2MD5_CLKCTRL  OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c8)
+#define OMAP5_DMA_CRYPTO_CLKCTRL       OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1d8)
+
 /* iva clocks */
 #define OMAP5_IVA_CLKCTRL      OMAP5_CLKCTRL_INDEX(0x20)
 #define OMAP5_SL2IF_CLKCTRL    OMAP5_CLKCTRL_INDEX(0x28)