clk: imx7ulp: do not export out IMX7ULP_CLK_MIPI_PLL clock

The mipi pll clock comes from the MIPI PHY PLL output, so
it should not be a fixed clock.

MIPI PHY PLL is in the MIPI DSI space, and it is used as
the bit clock for transferring the pixel data out and its
output clock is configured according to the display mode.

So it should be used only for MIPI DSI and not be exported
out for other usages.

Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
index a4f8cd478f924dfbeb2c52a78d01c3c4cfef465b..93d89adb7afe7b946b471b8f5e3b8986d2877924 100644 (file)
--- a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
@@ -82,7 +82,6 @@ pcc2: pcc2@403f0000 {
                 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
                 <&scg1 IMX7ULP_CLK_UPLL>,
                 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
-                <&scg1 IMX7ULP_CLK_MIPI_PLL>,
                 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
                 <&scg1 IMX7ULP_CLK_ROSC>,
                 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;

diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c
index c4b78a2d12b1e5346c49bbd3976e36edc2b7a319..3fdf3d494f0afc305c0212fb57914f1abbbf498c 100644 (file)
--- a/drivers/clk/imx/clk-imx7ulp.c
+++ b/drivers/clk/imx/clk-imx7ulp.c
@@ -28,7 +28,7 @@ static const char * const scs_sels[]          = { "dummy", "sosc", "sirc", "firc", "dumm
 static const char * const ddr_sels[]           = { "apll_pfd_sel", "dummy", "dummy", "dummy", };
 static const char * const nic_sels[]           = { "firc", "ddr_clk", };
 static const char * const periph_plat_sels[]   = { "dummy", "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", };
-static const char * const periph_bus_sels[]    = { "dummy", "sosc_bus_clk", "mpll", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", };
+static const char * const periph_bus_sels[]    = { "dummy", "sosc_bus_clk", "dummy", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", };
 static const char * const arm_sels[]           = { "divcore", "dummy", "dummy", "hsrun_divcore", };
 
 /* used by sosc/sirc/firc/ddr/spll/apll dividers */
@@ -75,7 +75,6 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np)
        clks[IMX7ULP_CLK_SOSC]          = imx_obtain_fixed_clk_hw(np, "sosc");
        clks[IMX7ULP_CLK_SIRC]          = imx_obtain_fixed_clk_hw(np, "sirc");
        clks[IMX7ULP_CLK_FIRC]          = imx_obtain_fixed_clk_hw(np, "firc");
-       clks[IMX7ULP_CLK_MIPI_PLL]      = imx_obtain_fixed_clk_hw(np, "mpll");
        clks[IMX7ULP_CLK_UPLL]          = imx_obtain_fixed_clk_hw(np, "upll");
 
        /* SCG1 */

diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h
index 6f66f9005c814bf3a6db2c66d845b373df9d0cc2..38145bdcd975228253d3e347cdf5ca8f2ddb3325 100644 (file)
--- a/include/dt-bindings/clock/imx7ulp-clock.h
+++ b/include/dt-bindings/clock/imx7ulp-clock.h
@@ -49,6 +49,7 @@
 #define IMX7ULP_CLK_NIC1_DIV           36
 #define IMX7ULP_CLK_NIC1_BUS_DIV       37
 #define IMX7ULP_CLK_NIC1_EXT_DIV       38
+/* IMX7ULP_CLK_MIPI_PLL is unsupported and shouldn't be used in DT */
 #define IMX7ULP_CLK_MIPI_PLL           39
 #define IMX7ULP_CLK_SIRC               40
 #define IMX7ULP_CLK_SOSC_BUS_CLK       41