pwm: ep93xx: Unfold legacy callbacks into ep93xx_pwm_apply()

This just puts the implementation of ep93xx_pwm_disable(),
ep93xx_pwm_enable() and ep93xx_pwm_config() into their only caller.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

diff --git a/drivers/pwm/pwm-ep93xx.c b/drivers/pwm/pwm-ep93xx.c
index 3ef4b41bfd6677be239adfbe3119cfc9f97f791e..3354b734f28f2882e7f94d33b93a58058796021a 100644 (file)
--- a/drivers/pwm/pwm-ep93xx.c
+++ b/drivers/pwm/pwm-ep93xx.c
@@ -58,138 +58,103 @@ static void ep93xx_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
        ep93xx_pwm_release_gpio(pdev);
 }
 
-static int ep93xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
-                            int duty_ns, int period_ns)
-{
-       struct ep93xx_pwm *ep93xx_pwm = to_ep93xx_pwm(chip);
-       void __iomem *base = ep93xx_pwm->base;
-       unsigned long long c;
-       unsigned long period_cycles;
-       unsigned long duty_cycles;
-       unsigned long term;
-       int ret = 0;
-
-       /*
-        * The clock needs to be enabled to access the PWM registers.
-        * Configuration can be changed at any time.
-        */
-       if (!pwm_is_enabled(pwm)) {
-               ret = clk_enable(ep93xx_pwm->clk);
-               if (ret)
-                       return ret;
-       }
-
-       c = clk_get_rate(ep93xx_pwm->clk);
-       c *= period_ns;
-       do_div(c, 1000000000);
-       period_cycles = c;
-
-       c = period_cycles;
-       c *= duty_ns;
-       do_div(c, period_ns);
-       duty_cycles = c;
-
-       if (period_cycles < 0x10000 && duty_cycles < 0x10000) {
-               term = readw(base + EP93XX_PWMx_TERM_COUNT);
-
-               /* Order is important if PWM is running */
-               if (period_cycles > term) {
-                       writew(period_cycles, base + EP93XX_PWMx_TERM_COUNT);
-                       writew(duty_cycles, base + EP93XX_PWMx_DUTY_CYCLE);
-               } else {
-                       writew(duty_cycles, base + EP93XX_PWMx_DUTY_CYCLE);
-                       writew(period_cycles, base + EP93XX_PWMx_TERM_COUNT);
-               }
-       } else {
-               ret = -EINVAL;
-       }
-
-       if (!pwm_is_enabled(pwm))
-               clk_disable(ep93xx_pwm->clk);
-
-       return ret;
-}
-
-static int ep93xx_pwm_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
-                              enum pwm_polarity polarity)
-{
-       struct ep93xx_pwm *ep93xx_pwm = to_ep93xx_pwm(chip);
-       int ret;
-
-       /*
-        * The clock needs to be enabled to access the PWM registers.
-        * Polarity can only be changed when the PWM is disabled.
-        */
-       ret = clk_enable(ep93xx_pwm->clk);
-       if (ret)
-               return ret;
-
-       if (polarity == PWM_POLARITY_INVERSED)
-               writew(0x1, ep93xx_pwm->base + EP93XX_PWMx_INVERT);
-       else
-               writew(0x0, ep93xx_pwm->base + EP93XX_PWMx_INVERT);
-
-       clk_disable(ep93xx_pwm->clk);
-
-       return 0;
-}
-
-static int ep93xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
-{
-       struct ep93xx_pwm *ep93xx_pwm = to_ep93xx_pwm(chip);
-       int ret;
-
-       ret = clk_enable(ep93xx_pwm->clk);
-       if (ret)
-               return ret;
-
-       writew(0x1, ep93xx_pwm->base + EP93XX_PWMx_ENABLE);
-
-       return 0;
-}
-
-static void ep93xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
-{
-       struct ep93xx_pwm *ep93xx_pwm = to_ep93xx_pwm(chip);
-
-       writew(0x0, ep93xx_pwm->base + EP93XX_PWMx_ENABLE);
-       clk_disable(ep93xx_pwm->clk);
-}
-
 static int ep93xx_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
                            const struct pwm_state *state)
 {
        int ret;
+       struct ep93xx_pwm *ep93xx_pwm = to_ep93xx_pwm(chip);
        bool enabled = state->enabled;
 
        if (state->polarity != pwm->state.polarity) {
                if (enabled) {
-                       ep93xx_pwm_disable(chip, pwm);
+                       writew(0x0, ep93xx_pwm->base + EP93XX_PWMx_ENABLE);
+                       clk_disable(ep93xx_pwm->clk);
                        enabled = false;
                }
 
-               ret = ep93xx_pwm_polarity(chip, pwm, state->polarity);
+               /*
+                * The clock needs to be enabled to access the PWM registers.
+                * Polarity can only be changed when the PWM is disabled.
+                */
+               ret = clk_enable(ep93xx_pwm->clk);
                if (ret)
                        return ret;
+
+               if (state->polarity == PWM_POLARITY_INVERSED)
+                       writew(0x1, ep93xx_pwm->base + EP93XX_PWMx_INVERT);
+               else
+                       writew(0x0, ep93xx_pwm->base + EP93XX_PWMx_INVERT);
+
+               clk_disable(ep93xx_pwm->clk);
        }
 
        if (!state->enabled) {
-               if (enabled)
-                       ep93xx_pwm_disable(chip, pwm);
+               if (enabled) {
+                       writew(0x0, ep93xx_pwm->base + EP93XX_PWMx_ENABLE);
+                       clk_disable(ep93xx_pwm->clk);
+               }
 
                return 0;
        }
 
        if (state->period != pwm->state.period ||
            state->duty_cycle != pwm->state.duty_cycle) {
-               ret = ep93xx_pwm_config(chip, pwm, (int)state->duty_cycle,
-                                       (int)state->period);
+               struct ep93xx_pwm *ep93xx_pwm = to_ep93xx_pwm(chip);
+               void __iomem *base = ep93xx_pwm->base;
+               unsigned long long c;
+               unsigned long period_cycles;
+               unsigned long duty_cycles;
+               unsigned long term;
+
+               /*
+                * The clock needs to be enabled to access the PWM registers.
+                * Configuration can be changed at any time.
+                */
+               if (!pwm_is_enabled(pwm)) {
+                       ret = clk_enable(ep93xx_pwm->clk);
+                       if (ret)
+                               return ret;
+               }
+
+               c = clk_get_rate(ep93xx_pwm->clk);
+               c *= state->period;
+               do_div(c, 1000000000);
+               period_cycles = c;
+
+               c = period_cycles;
+               c *= state->duty_cycle;
+               do_div(c, state->period);
+               duty_cycles = c;
+
+               if (period_cycles < 0x10000 && duty_cycles < 0x10000) {
+                       term = readw(base + EP93XX_PWMx_TERM_COUNT);
+
+                       /* Order is important if PWM is running */
+                       if (period_cycles > term) {
+                               writew(period_cycles, base + EP93XX_PWMx_TERM_COUNT);
+                               writew(duty_cycles, base + EP93XX_PWMx_DUTY_CYCLE);
+                       } else {
+                               writew(duty_cycles, base + EP93XX_PWMx_DUTY_CYCLE);
+                               writew(period_cycles, base + EP93XX_PWMx_TERM_COUNT);
+                       }
+               } else {
+                       ret = -EINVAL;
+               }
+
+               if (!pwm_is_enabled(pwm))
+                       clk_disable(ep93xx_pwm->clk);
+
                if (ret)
                        return ret;
        }
 
-       if (!enabled)
-               return ep93xx_pwm_enable(chip, pwm);
+       if (!enabled) {
+               ret = clk_enable(ep93xx_pwm->clk);
+               if (ret)
+                       return ret;
+
+               writew(0x1, ep93xx_pwm->base + EP93XX_PWMx_ENABLE);
+       }
 
        return 0;
 }