void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
 {
-       if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
+       int ret = 0;
+       if (is_support_sw_smu(adev)) {
+           ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_UVD, enable);
+           if (ret)
+               DRM_ERROR("[SW SMU]: dpm enable uvd failed, state = %s, ret = %d. \n",
+                         enable ? "true" : "false", ret);
+       } else if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
                /* enable/disable UVD */
                mutex_lock(&adev->pm.mutex);
                amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
 
 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
 {
-       if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
+       int ret = 0;
+       if (is_support_sw_smu(adev)) {
+           ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_VCE, enable);
+           if (ret)
+               DRM_ERROR("[SW SMU]: dpm enable vce failed, state = %s, ret = %d. \n",
+                         enable ? "true" : "false", ret);
+       } else if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
                /* enable/disable VCE */
                mutex_lock(&adev->pm.mutex);
                amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
 
 #include "smu_v11_0.h"
 #include "atom.h"
 
+int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
+                          bool gate)
+{
+       int ret = 0;
+
+       switch (block_type) {
+       case AMD_IP_BLOCK_TYPE_UVD:
+               ret = smu_dpm_set_uvd_enable(smu, gate);
+               break;
+       case AMD_IP_BLOCK_TYPE_VCE:
+               ret = smu_dpm_set_vce_enable(smu, gate);
+               break;
+       default:
+               break;
+       }
+
+       return ret;
+}
+
 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
 {
        /* not support power state */