arm64: dts: ti: k3-j721e-som-p0/common-proc-board: Fixup reference to phandles array
authorNishanth Menon <nm@ti.com>
Tue, 6 Jun 2023 18:22:08 +0000 (13:22 -0500)
committerVignesh Raghavendra <vigneshr@ti.com>
Thu, 15 Jun 2023 05:35:47 +0000 (11:05 +0530)
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.

Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi

index fa6ac3475290c9d138d0e7775a34f1e99fcc0a39..2d5d75fffde9b1e8015c0b6895ad57596706cc45 100644 (file)
@@ -23,7 +23,7 @@
                compatible = "gpio-keys";
                autorepeat;
                pinctrl-names = "default";
-               pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>;
+               pinctrl-0 = <&sw10_button_pins_default>, <&sw11_button_pins_default>;
 
                sw10: switch-10 {
                        label = "GPIO Key USER1";
 
 &mcu_cpsw {
        pinctrl-names = "default";
-       pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+       pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
 };
 
 &davinci_mdio {
index 67e52ee3a8bda1e9a249e24ecaf4ebba0a57dbad..7a4c00ca93718c59c8fb0fc7c89124ce716673c2 100644 (file)
 };
 
 &mcu_r5fss0_core0 {
-       mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+       mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
        memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
                        <&mcu_r5fss0_core0_memory_region>;
 };
 
 &mcu_r5fss0_core1 {
-       mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+       mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
        memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
                        <&mcu_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss0_core0 {
-       mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+       mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
        memory-region = <&main_r5fss0_core0_dma_memory_region>,
                        <&main_r5fss0_core0_memory_region>;
 };
 
 &main_r5fss0_core1 {
-       mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+       mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
        memory-region = <&main_r5fss0_core1_dma_memory_region>,
                        <&main_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss1_core0 {
-       mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
+       mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
        memory-region = <&main_r5fss1_core0_dma_memory_region>,
                        <&main_r5fss1_core0_memory_region>;
 };
 
 &main_r5fss1_core1 {
-       mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
+       mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
        memory-region = <&main_r5fss1_core1_dma_memory_region>,
                        <&main_r5fss1_core1_memory_region>;
 };
 
 &c66_0 {
-       mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
+       mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
        memory-region = <&c66_0_dma_memory_region>,
                        <&c66_0_memory_region>;
 };
 
 &c66_1 {
-       mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
+       mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
        memory-region = <&c66_1_dma_memory_region>,
                        <&c66_1_memory_region>;
 };
 
 &c71_0 {
-       mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+       mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
        memory-region = <&c71_0_dma_memory_region>,
                        <&c71_0_memory_region>;
 };