ARM: dts: imx6sx-sdb: Add MQS support
authorShengjiu Wang <shengjiu.wang@nxp.com>
Sun, 12 Jul 2020 09:16:42 +0000 (17:16 +0800)
committerShawn Guo <shawnguo@kernel.org>
Mon, 13 Jul 2020 11:48:53 +0000 (19:48 +0800)
Add MQS support. As the pin conflict with usdhc2, then need
to add a separate dts.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm/boot/dts/Makefile
arch/arm/boot/dts/imx6sx-sdb-mqs.dts [new file with mode: 0644]
arch/arm/boot/dts/imx6sx-sdb.dtsi
arch/arm/boot/dts/imx6sx.dtsi

index e6a1cac0bfc707ac887081f99ce39469d9a4853d..04f85d6a2af39ca11260aedefa4d015b226b1f33 100644 (file)
@@ -592,6 +592,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
        imx6sx-sdb-reva.dtb \
        imx6sx-sdb-sai.dtb \
        imx6sx-sdb.dtb \
+       imx6sx-sdb-mqs.dtb \
        imx6sx-softing-vining-2000.dtb \
        imx6sx-udoo-neo-basic.dtb \
        imx6sx-udoo-neo-extended.dtb \
diff --git a/arch/arm/boot/dts/imx6sx-sdb-mqs.dts b/arch/arm/boot/dts/imx6sx-sdb-mqs.dts
new file mode 100644 (file)
index 0000000..a4ab2d3
--- /dev/null
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2014 Freescale Semiconductor, Inc.
+
+#include "imx6sx-sdb.dts"
+/ {
+
+       sound {
+               status = "disabled";
+       };
+
+       sound-mqs {
+               compatible = "fsl,imx6sx-sdb-mqs",
+                            "fsl,imx-audio-mqs";
+               model = "mqs-audio";
+               audio-cpu = <&sai1>;
+               audio-asrc = <&asrc>;
+               audio-codec = <&mqs>;
+       };
+};
+
+&usdhc2 {
+       /* pin conflict with mqs*/
+       status = "disabled";
+};
+
+&mqs {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_mqs>;
+       clocks = <&clks IMX6SX_CLK_SAI1>;
+       clock-names = "mclk";
+       status = "okay";
+};
+
+&sai1 {
+       pinctrl-0 = <>;
+       status = "okay";
+};
+
+&ssi2 {
+       status = "disabled";
+};
+
+&sdma {
+       gpr = <&gpr>;
+       /* SDMA event remap for SAI1 */
+       fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
+};
index 6673532018b2625ddc93f28f4202946a62207c57..05d1e9d2efab543019d43a7991f520ce99ed48a4 100644 (file)
                        >;
                };
 
+               pinctrl_mqs: mqsgrp {
+                       fsl,pins = <
+                               MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0
+                               MX6SX_PAD_SD2_CMD__MQS_LEFT  0x120b0
+                       >;
+               };
+
                pinctrl_pcie: pciegrp {
                        fsl,pins = <
                                MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0
index 5c2b78589aa5425b7047df4b0ec85ce83def2e4a..fcb3d064d0ccc53f62ffb0ca3de1b0fc35665422 100644 (file)
                clock-output-names = "anaclk2";
        };
 
+       mqs: mqs {
+               compatible = "fsl,imx6sx-mqs";
+               gpr = <&gpr>;
+               status = "disabled";
+       };
+
        pmu {
                compatible = "arm,cortex-a9-pmu";
                interrupt-parent = <&gpc>;