PCI: qcom: Add support for SDX55 SoC

Add support for SDX55 SoC reusing the 1.9.0 config. The PCIe controller is
of version 1.10.0 but it is compatible with the 1.9.0 config. This SoC also
requires "sleep" clock which is added as an optional clock in the driver,
since it is not required on other SoCs.

Link: https://lore.kernel.org/r/20230308082424.140224-14-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 9791af8b09f392541a6efbbe5a71ff4a37454a6d..ecd6d1e466664b74d12333cdf4608de34b908fcc 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -193,7 +193,7 @@ struct qcom_pcie_resources_2_4_0 {
        int num_resets;
 };
 
-#define QCOM_PCIE_2_7_0_MAX_CLOCKS             12
+#define QCOM_PCIE_2_7_0_MAX_CLOCKS             13
 #define QCOM_PCIE_2_7_0_MAX_SUPPLIES           2
 struct qcom_pcie_resources_2_7_0 {
        struct clk_bulk_data clks[QCOM_PCIE_2_7_0_MAX_CLOCKS];
@@ -879,6 +879,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
        res->clks[idx++].id = "noc_aggr_4";
        res->clks[idx++].id = "noc_aggr_south_sf";
        res->clks[idx++].id = "cnoc_qx";
+       res->clks[idx++].id = "sleep";
 
        num_opt_clks = idx - num_clks;
        res->num_clks = idx;
@@ -1611,6 +1612,7 @@ static const struct of_device_id qcom_pcie_match[] = {
        { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 },
        { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_1_9_0 },
        { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 },
+       { .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 },
        { .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 },
        { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 },
        { .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 },