arm64: dts: renesas: r9a09g011: Add pinctrl node

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220804190846.128370-1-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
index d4cc5459fbb76d62149f19e70836fcbe39bf8ba6..44e1e288343c4ffc0acf2feaad038d2c76be6832 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
@@ -132,6 +132,56 @@
                        clock-names = "sclk", "pclk";
                        status = "disabled";
                };
+
+               pinctrl: pinctrl@b6250000 {
+                       compatible = "renesas,r9a09g011-pinctrl";
+                       reg = <0 0xb6250000 0 0x800>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&pinctrl 0 0 352>;
+                       interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD R9A09G011_PFC_PCLK>;
+                       power-domains = <&cpg>;
+                       resets = <&cpg R9A09G011_PFC_PRESETN>;
+               };
        };
 
        timer {