return "UNKNOWN";
 }
 
+void panfrost_device_reset(struct panfrost_device *pfdev)
+{
+       panfrost_gpu_soft_reset(pfdev);
+
+       panfrost_gpu_power_on(pfdev);
+       panfrost_mmu_reset(pfdev);
+       panfrost_job_enable_interrupts(pfdev);
+}
+
 #ifdef CONFIG_PM
 int panfrost_device_resume(struct device *dev)
 {
        struct platform_device *pdev = to_platform_device(dev);
        struct panfrost_device *pfdev = platform_get_drvdata(pdev);
 
-       panfrost_gpu_soft_reset(pfdev);
-
-       /* TODO: Re-enable all other address spaces */
-       panfrost_gpu_power_on(pfdev);
-       panfrost_mmu_enable(pfdev, 0);
-       panfrost_job_enable_interrupts(pfdev);
+       panfrost_device_reset(pfdev);
        panfrost_devfreq_resume(pfdev);
 
        return 0;
 
        /* panfrost_core_dump(pfdev); */
 
        panfrost_devfreq_record_transition(pfdev, js);
-       panfrost_gpu_soft_reset(pfdev);
-
-       /* TODO: Re-enable all other address spaces */
-       panfrost_mmu_enable(pfdev, 0);
-       panfrost_gpu_power_on(pfdev);
-       panfrost_job_enable_interrupts(pfdev);
+       panfrost_device_reset(pfdev);
 
        for (i = 0; i < NUM_JOB_SLOTS; i++)
                drm_sched_resubmit_jobs(&pfdev->js->queue[i].sched);
 
        return ret;
 }
 
-void panfrost_mmu_enable(struct panfrost_device *pfdev, u32 as_nr)
+static void panfrost_mmu_enable(struct panfrost_device *pfdev, u32 as_nr)
 {
        struct io_pgtable_cfg *cfg = &pfdev->mmu->pgtbl_cfg;
        u64 transtab = cfg->arm_mali_lpae_cfg.transtab;
        u64 memattr = cfg->arm_mali_lpae_cfg.memattr;
 
-       mmu_write(pfdev, MMU_INT_CLEAR, ~0);
-       mmu_write(pfdev, MMU_INT_MASK, ~0);
-
        mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), transtab & 0xffffffffUL);
        mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), transtab >> 32);
 
        write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE);
 }
 
+void panfrost_mmu_reset(struct panfrost_device *pfdev)
+{
+       panfrost_mmu_enable(pfdev, 0);
+
+       mmu_write(pfdev, MMU_INT_CLEAR, ~0);
+       mmu_write(pfdev, MMU_INT_MASK, ~0);
+}
+
 static size_t get_pgsize(u64 addr, size_t size)
 {
        if (addr & (SZ_2M - 1) || size < SZ_2M)
                dev_err(pfdev->dev, "failed to request mmu irq");
                return err;
        }
-       mmu_write(pfdev, MMU_INT_CLEAR, ~0);
-       mmu_write(pfdev, MMU_INT_MASK, ~0);
-
        pfdev->mmu->pgtbl_cfg = (struct io_pgtable_cfg) {
                .pgsize_bitmap  = SZ_4K | SZ_2M,
                .ias            = FIELD_GET(0xff, pfdev->features.mmu_features),