arm64: dts: qcom: sm8550: Fix UFS PHY clocks

QMP PHY used in SM8550 requires 3 clocks:

* ref - 19.2MHz reference clock from RPMh
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from TCSR

Fixes: 35cf1aaab169 ("arm64: dts: qcom: sm8550: Add UFS host controller and phy nodes")
Reviewed-by: Can Guo <quic_cang@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-16-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index f9a6c63ebc0999beb6f171c425113e75d6df0f3c..b8f1c7f97e481e8f8da4397be47a89d85bc670ab 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1933,9 +1933,12 @@
                ufs_mem_phy: phy@1d80000 {
                        compatible = "qcom,sm8550-qmp-ufs-phy";
                        reg = <0x0 0x01d80000 0x0 0x2000>;
-                       clocks = <&tcsr TCSR_UFS_CLKREF_EN>,
-                                <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
-                       clock-names = "ref", "ref_aux";
+                       clocks = <&rpmhcc RPMH_CXO_CLK>,
+                                <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+                                <&tcsr TCSR_UFS_CLKREF_EN>;
+                       clock-names = "ref",
+                                     "ref_aux",
+                                     "qref";
 
                        power-domains = <&gcc UFS_MEM_PHY_GDSC>;