Merge branches 'clk-qcom-alpha-pll', 'clk-check-ops-ptr', 'clk-protect-rate' and...

* clk-qcom-alpha-pll:
  clk: qcom: add read-only alpha pll post divider operations
  clk: qcom: support for 2 bit PLL post divider
  clk: qcom: support Brammo type Alpha PLL
  clk: qcom: support Huayra type Alpha PLL
  clk: qcom: support for dynamic updating the PLL
  clk: qcom: support for alpha mode configuration
  clk: qcom: flag for 64 bit CONFIG_CTL
  clk: qcom: fix 16 bit alpha support calculation
  clk: qcom: support for alpha pll properties

* clk-check-ops-ptr:
  clk: check ops pointer on clock register

* clk-protect-rate:
  clk: fix set_rate_range when current rate is out of range
  clk: add clk_rate_exclusive api
  clk: cosmetic changes to clk_summary debugfs entry
  clk: add clock protection mechanism to clk core
  clk: use round rate to bail out early in set_rate
  clk: rework calls to round and determine rate callbacks
  clk: add clk_core_set_phase_nolock function
  clk: take the prepare lock out of clk_core_set_parent
  clk: fix incorrect usage of ENOSYS

* clk-omap:
  clk: ti: Drop legacy clk-3xxx-legacy code

diff --cc drivers/clk/clk.c
index 8a1860a36c778aba3b66de996a6cc7ee878cf97e,647d056df88c8dd2a7d8288e35fa2eeba9b7705b,e3e98acab2c069f4e32f16d40b2df3dd84b55f40,efbc802da3b3020dfcbe39ceea0b5c523a011ea3,647d056df88c8dd2a7d8288e35fa2eeba9b7705b..3526bc068f306441349c899de0b1b3c4234a755d
--- 1/drivers/clk/clk.c
--- 2/drivers/clk/clk.c
--- 3/drivers/clk/clk.c
--- 4/drivers/clk/clk.c
--- 5/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@@@@@ -934,15 -934,15 -934,15 -1077,58 -934,15 +1077,58 @@@@@@ static int clk_core_determine_round_nol
                        return rate;
     
                req->rate = rate;
--- -   } else if (core->flags & CLK_SET_RATE_PARENT) {
--- -           return clk_core_round_rate_nolock(parent, req);
        } else {
--- -           req->rate = core->rate;
+++ +           return -EINVAL;
 +  +   }
 +  +
 +  +   return 0;
 +  +}
 +  +
+++ +static void clk_core_init_rate_req(struct clk_core * const core,
+++ +                              struct clk_rate_request *req)
+++ +{
+++ +   struct clk_core *parent;
+++ +
+++ +   if (WARN_ON(!core || !req))
+++ +           return;
+++ +
+++ +   parent = core->parent;
+++ +   if (parent) {
+++ +           req->best_parent_hw = parent->hw;
+++ +           req->best_parent_rate = parent->rate;
+++ +   } else {
+++ +           req->best_parent_hw = NULL;
+++ +           req->best_parent_rate = 0;
+ +     }
+++ +}
+ +  
+++ +static bool clk_core_can_round(struct clk_core * const core)
+++ +{
+++ +   if (core->ops->determine_rate || core->ops->round_rate)
+++ +           return true;
+++ +
+++ +   return false;
+++ +}
+++ +
+++ +static int clk_core_round_rate_nolock(struct clk_core *core,
+++ +                                 struct clk_rate_request *req)
+++ +{
+++ +   lockdep_assert_held(&prepare_lock);
+++ +
+++ +   if (!core)
+++ +           return 0;
+++ +
+++ +   clk_core_init_rate_req(core, req);
+++ +
+++ +   if (clk_core_can_round(core))
+++ +           return clk_core_determine_round_nolock(core, req);
+++ +   else if (core->flags & CLK_SET_RATE_PARENT)
+++ +           return clk_core_round_rate_nolock(core->parent, req);
+++ +
+++ +   req->rate = core->rate;
+ +     return 0;
+ +  }
+ +  
     /**
      * __clk_determine_rate - get the closest rate actually supported by a clock
      * @hw: determine the rate of this clock
@@@@@@ -1637,10 -1634,8 -1634,8 -1816,35 -1634,8 +1819,37 @@@@@@ static void clk_change_rate(struct clk_
        /* handle the new child who might not be in core->children yet */
        if (core->new_child)
                clk_change_rate(core->new_child);
 ++++
 ++++   clk_pm_runtime_put(core);
 ++ +}
 ++ +
+++ +static unsigned long clk_core_req_round_rate_nolock(struct clk_core *core,
+++ +                                                unsigned long req_rate)
+++ +{
+++ +   int ret, cnt;
+++ +   struct clk_rate_request req;
+++ +
+++ +   lockdep_assert_held(&prepare_lock);
+++ +
+++ +   if (!core)
+++ +           return 0;
+++ +
+++ +   /* simulate what the rate would be if it could be freely set */
+++ +   cnt = clk_core_rate_nuke_protect(core);
+++ +   if (cnt < 0)
+++ +           return cnt;
+++ +
+++ +   clk_core_get_boundaries(core, &req.min_rate, &req.max_rate);
+++ +   req.rate = req_rate;
+++ +
+++ +   ret = clk_core_round_rate_nolock(core, &req);
+++ +
+++ +   /* restore the protection */
+++ +   clk_core_rate_restore_protect(core, cnt);
+++ +
+++ +   return ret ? 0 : req.rate;
+    }
+    
     static int clk_core_set_rate_nolock(struct clk_core *core,
                                    unsigned long req_rate)
     {
@@@@@@ -2005,15 -2000,15 -2000,15 -2336,13 -2000,15 +2341,13 @@@@@@ int clk_set_phase(struct clk *clk, int 
     
        clk_prepare_lock();
     
--- -   trace_clk_set_phase(clk->core, degrees);
 -  -
 -  -   if (clk->core->ops->set_phase)
 -  -           ret = clk->core->ops->set_phase(clk->core->hw, degrees);
+++ +   if (clk->exclusive_count)
+++ +           clk_core_rate_unprotect(clk->core);
     
- -     if (clk->core->ops->set_phase)
- -             ret = clk->core->ops->set_phase(clk->core->hw, degrees);
 -  -   trace_clk_set_phase_complete(clk->core, degrees);
+++ +   ret = clk_core_set_phase_nolock(clk->core, degrees);
     
- -     trace_clk_set_phase_complete(clk->core, degrees);
- -  
--- -   if (!ret)
--- -           clk->core->phase = degrees;
+++ +   if (clk->exclusive_count)
+++ +           clk_core_rate_protect(clk->core);
     
        clk_prepare_unlock();
     

diff --cc drivers/clk/ti/clock.h
index 883e39e5d3ec08648d79a60710182617d3477787,561dbe99ced72122b5b33a808830c0706891a01d,561dbe99ced72122b5b33a808830c0706891a01d,561dbe99ced72122b5b33a808830c0706891a01d,1654da96ad651b46524d1dc07285dc0a88070e6c..d9b43bfc25325687302876374d8e9e337a315eec
--- 1/drivers/clk/ti/clock.h
--- 2/drivers/clk/ti/clock.h
--- 3/drivers/clk/ti/clock.h
--- 4/drivers/clk/ti/clock.h
--- 5/drivers/clk/ti/clock.h
+++ b/drivers/clk/ti/clock.h
@@@@@@ -243,14 -234,14 -234,14 -234,14 -179,8 +187,8 @@@@@@ extern const struct omap_clkctrl_data d
     #define CLKF_HW_SUP        BIT(1)
     #define CLKF_NO_IDLEST     BIT(2)
     
 --- typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *);
 +++ typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *);
     
---- struct clk *ti_clk_register_gate(struct ti_clk *setup);
---- struct clk *ti_clk_register_interface(struct ti_clk *setup);
---- struct clk *ti_clk_register_mux(struct ti_clk *setup);
---- struct clk *ti_clk_register_divider(struct ti_clk *setup);
---- struct clk *ti_clk_register_composite(struct ti_clk *setup);
---- struct clk *ti_clk_register_dpll(struct ti_clk *setup);
     struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
                            const char *con);
     int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con);