watchdog: aspeed: Fix sequential control writes
authorAndrew Jeffery <andrew@aj.id.au>
Mon, 20 Sep 2021 06:50:59 +0000 (08:50 +0200)
committerCédric Le Goater <clg@kaod.org>
Mon, 20 Sep 2021 06:50:59 +0000 (08:50 +0200)
The logic in the handling for the control register required toggling the
enable state for writes to stick. Rework the condition chain to allow
sequential writes that do not update the enable state.

Fixes: 854123bf8d4b ("wdt: Add Aspeed watchdog device model")
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210709053107.1829304-3-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
hw/watchdog/wdt_aspeed.c

index faa3d35fdf2188a8c715a21153ea9c1f9746edc8..69c37af9a6e9a56505c19b6ff687b296b535604e 100644 (file)
@@ -166,6 +166,8 @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,
         } else if (!enable && aspeed_wdt_is_enabled(s)) {
             s->regs[WDT_CTRL] = data;
             timer_del(s->timer);
+        } else {
+            s->regs[WDT_CTRL] = data;
         }
         break;
     case WDT_RESET_WIDTH: