mfd: intel-m10-bmc: Change staging size to a variable
authorIlpo Järvinen <ilpo.jarvinen@linux.intel.com>
Tue, 2 Apr 2024 18:49:25 +0000 (14:49 -0400)
committerLee Jones <lee@kernel.org>
Fri, 10 May 2024 14:39:16 +0000 (15:39 +0100)
The secure update driver does a sanity-check of the image size in
comparison to the size of the staging area in FLASH. Instead of
hard-wiring M10BMC_STAGING_SIZE, move the staging size to the
m10bmc_csr_map structure to make the size assignment more flexible.

Co-developed-by: Russ Weight <russell.h.weight@intel.com>
Signed-off-by: Russ Weight <russell.h.weight@intel.com>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Peter Colberg <peter.colberg@intel.com>
Reviewed-by: Xu Yilun <yilun.xu@intel.com>
Link: https://lore.kernel.org/r/20240402184925.1065932-1-peter.colberg@intel.com
Signed-off-by: Lee Jones <lee@kernel.org>
drivers/fpga/intel-m10-bmc-sec-update.c
drivers/mfd/intel-m10-bmc-pmci.c
drivers/mfd/intel-m10-bmc-spi.c
include/linux/mfd/intel-m10-bmc.h

index 89851b1337097c0a58750a5feaa4dbdd4bd12f86..7ac9f9f5af129bcc5674c5891e11a6378e5744ee 100644 (file)
@@ -529,11 +529,12 @@ static enum fw_upload_err m10bmc_sec_prepare(struct fw_upload *fwl,
                                             const u8 *data, u32 size)
 {
        struct m10bmc_sec *sec = fwl->dd_handle;
+       const struct m10bmc_csr_map *csr_map = sec->m10bmc->info->csr_map;
        u32 ret;
 
        sec->cancel_request = false;
 
-       if (!size || size > M10BMC_STAGING_SIZE)
+       if (!size || size > csr_map->staging_size)
                return FW_UPLOAD_ERR_INVALID_SIZE;
 
        if (sec->m10bmc->flash_bulk_ops)
index 0392ef8b57d860bd2913844cd0edc4c0df46725e..698c5933938b79bc86884f2c9dbab5cca1de2e3b 100644 (file)
@@ -370,6 +370,7 @@ static const struct m10bmc_csr_map m10bmc_n6000_csr_map = {
        .pr_reh_addr = M10BMC_N6000_PR_REH_ADDR,
        .pr_magic = M10BMC_N6000_PR_PROG_MAGIC,
        .rsu_update_counter = M10BMC_N6000_STAGING_FLASH_COUNT,
+       .staging_size = M10BMC_STAGING_SIZE,
 };
 
 static const struct intel_m10bmc_platform_info m10bmc_pmci_n6000 = {
index cbeb7de9e04160935a83796c95f5d27ed2d4e337..d64d28199df656557aaec6c27522352bf995a9c3 100644 (file)
@@ -109,6 +109,7 @@ static const struct m10bmc_csr_map m10bmc_n3000_csr_map = {
        .pr_reh_addr = M10BMC_N3000_PR_REH_ADDR,
        .pr_magic = M10BMC_N3000_PR_PROG_MAGIC,
        .rsu_update_counter = M10BMC_N3000_STAGING_FLASH_COUNT,
+       .staging_size = M10BMC_STAGING_SIZE,
 };
 
 static struct mfd_cell m10bmc_d5005_subdevs[] = {
index ee66c9751003de3a2bf281e75c8324271a7e35d7..988f1cd90032f28a012380feebaf12c595bb9d23 100644 (file)
@@ -205,6 +205,7 @@ struct m10bmc_csr_map {
        unsigned int pr_reh_addr;
        unsigned int pr_magic;
        unsigned int rsu_update_counter;
+       unsigned int staging_size;
 };
 
 /**