ARM64: dts: meson-gx: add VPU power domain

This patch adds support for the VPU Power Domain nodes, and attaches the
VPU power domain to the VPU node.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index ab7ce1644cdc59f2797323f8c83d34c1e3594a9a..668d891b23a0fb8a88fedd58628e781242b0a6f5 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -377,6 +377,12 @@
                                compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
                                reg =  <0x0 0x0 0x0 0x100>;
 
+                               pwrc_vpu: power-controller-vpu {
+                                       compatible = "amlogic,meson-gx-pwrc-vpu";
+                                       #power-domain-cells = <0>;
+                                       amlogic,hhi-sysctrl = <&sysctrl>;
+                               };
+
                                clkc_AO: clock-controller {
                                        compatible = "amlogic,meson-gx-aoclkc";
                                        #clock-cells = <1>;
@@ -454,6 +460,11 @@
                        #size-cells = <2>;
                        ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
 
+                       sysctrl: system-controller@0 {
+                               compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";
+                               reg = <0 0 0 0x400>;
+                       };
+
                        mailbox: mailbox@404 {
                                compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
                                reg = <0 0x404 0 0x4c>;

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index ead895a4e9a5c9fb6f663092288e8178b95cd6a1..6904872f08af56d3b8d8edfc7f6298b30f6ba56c 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -694,6 +694,48 @@
        };
 };
 
+&pwrc_vpu {
+       resets = <&reset RESET_VIU>,
+                <&reset RESET_VENC>,
+                <&reset RESET_VCBUS>,
+                <&reset RESET_BT656>,
+                <&reset RESET_DVIN_RESET>,
+                <&reset RESET_RDMA>,
+                <&reset RESET_VENCI>,
+                <&reset RESET_VENCP>,
+                <&reset RESET_VDAC>,
+                <&reset RESET_VDI6>,
+                <&reset RESET_VENCL>,
+                <&reset RESET_VID_LOCK>;
+       clocks = <&clkc CLKID_VPU>,
+                <&clkc CLKID_VAPB>;
+       clock-names = "vpu", "vapb";
+       /*
+        * VPU clocking is provided by two identical clock paths
+        * VPU_0 and VPU_1 muxed to a single clock by a glitch
+        * free mux to safely change frequency while running.
+        * Same for VAPB but with a final gate after the glitch free mux.
+        */
+       assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
+                         <&clkc CLKID_VPU_0>,
+                         <&clkc CLKID_VPU>, /* Glitch free mux */
+                         <&clkc CLKID_VAPB_0_SEL>,
+                         <&clkc CLKID_VAPB_0>,
+                         <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
+       assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+                                <0>, /* Do Nothing */
+                                <&clkc CLKID_VPU_0>,
+                                <&clkc CLKID_FCLK_DIV4>,
+                                <0>, /* Do Nothing */
+                                <&clkc CLKID_VAPB_0>;
+       assigned-clock-rates = <0>, /* Do Nothing */
+                              <666666666>,
+                              <0>, /* Do Nothing */
+                              <0>, /* Do Nothing */
+                              <250000000>,
+                              <0>; /* Do Nothing */
+};
+
 &saradc {
        compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
        clocks = <&xtal>,
@@ -763,4 +805,5 @@
 
 &vpu {
        compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
+       power-domains = <&pwrc_vpu>;
 };

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index 8ed981f59e5ae5804da97c887193a32a73b53983..49b8ec159603cd709eb4c43e0352e9a68198f36e 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -644,6 +644,48 @@
        };
 };
 
+&pwrc_vpu {
+       resets = <&reset RESET_VIU>,
+                <&reset RESET_VENC>,
+                <&reset RESET_VCBUS>,
+                <&reset RESET_BT656>,
+                <&reset RESET_DVIN_RESET>,
+                <&reset RESET_RDMA>,
+                <&reset RESET_VENCI>,
+                <&reset RESET_VENCP>,
+                <&reset RESET_VDAC>,
+                <&reset RESET_VDI6>,
+                <&reset RESET_VENCL>,
+                <&reset RESET_VID_LOCK>;
+       clocks = <&clkc CLKID_VPU>,
+                <&clkc CLKID_VAPB>;
+       clock-names = "vpu", "vapb";
+       /*
+        * VPU clocking is provided by two identical clock paths
+        * VPU_0 and VPU_1 muxed to a single clock by a glitch
+        * free mux to safely change frequency while running.
+        * Same for VAPB but with a final gate after the glitch free mux.
+        */
+       assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
+                         <&clkc CLKID_VPU_0>,
+                         <&clkc CLKID_VPU>, /* Glitch free mux */
+                         <&clkc CLKID_VAPB_0_SEL>,
+                         <&clkc CLKID_VAPB_0>,
+                         <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
+       assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+                                <0>, /* Do Nothing */
+                                <&clkc CLKID_VPU_0>,
+                                <&clkc CLKID_FCLK_DIV4>,
+                                <0>, /* Do Nothing */
+                                <&clkc CLKID_VAPB_0>;
+       assigned-clock-rates = <0>, /* Do Nothing */
+                              <666666666>,
+                              <0>, /* Do Nothing */
+                              <0>, /* Do Nothing */
+                              <250000000>,
+                              <0>; /* Do Nothing */
+};
+
 &saradc {
        compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
        clocks = <&xtal>,
@@ -713,4 +755,5 @@
 
 &vpu {
        compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
+       power-domains = <&pwrc_vpu>;
 };