riscv: dts: starfive: Add spi node and pins configuration

Add StarFive JH7110 SPI controller node and pins configuration on
VisionFive 2 board.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 36c402b4a726cdfdaa6d0c32385bad13c8239a08..dc3450e06d29a706e74a4915d80eaab0f90b9785 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -185,6 +185,18 @@
        status = "okay";
 };
 
+&spi0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&spi0_pins>;
+       status = "okay";
+
+       spi_dev0: spi@0 {
+               compatible = "rohm,dh2228fv";
+               reg = <0>;
+               spi-max-frequency = <10000000>;
+       };
+};
+
 &sysgpio {
        i2c0_pins: i2c0-0 {
                i2c-pins {
@@ -242,6 +254,44 @@
                };
        };
 
+       spi0_pins: spi0-0 {
+               mosi-pins {
+                       pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
+                                             GPOEN_ENABLE,
+                                             GPI_NONE)>;
+                       bias-disable;
+                       input-disable;
+                       input-schmitt-disable;
+               };
+
+               miso-pins {
+                       pinmux = <GPIOMUX(53, GPOUT_LOW,
+                                             GPOEN_DISABLE,
+                                             GPI_SYS_SPI0_RXD)>;
+                       bias-pull-up;
+                       input-enable;
+                       input-schmitt-enable;
+               };
+
+               sck-pins {
+                       pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK,
+                                             GPOEN_ENABLE,
+                                             GPI_SYS_SPI0_CLK)>;
+                       bias-disable;
+                       input-disable;
+                       input-schmitt-disable;
+               };
+
+               ss-pins {
+                       pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_FSS,
+                                             GPOEN_ENABLE,
+                                             GPI_SYS_SPI0_FSS)>;
+                       bias-disable;
+                       input-disable;
+                       input-schmitt-disable;
+               };
+       };
+
        uart0_pins: uart0-0 {
                tx-pins {
                        pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index c58489468cad52eb6cd563c83255603144702c87..ecd4160b2f5425a5b6ddf927a0f9e47507520de9 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -446,6 +446,51 @@
                        status = "disabled";
                };
 
+               spi0: spi@10060000 {
+                       compatible = "arm,pl022", "arm,primecell";
+                       reg = <0x0 0x10060000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_SPI0_APB>,
+                                <&syscrg JH7110_SYSCLK_SPI0_APB>;
+                       clock-names = "sspclk", "apb_pclk";
+                       resets = <&syscrg JH7110_SYSRST_SPI0_APB>;
+                       interrupts = <38>;
+                       arm,primecell-periphid = <0x00041022>;
+                       num-cs = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               spi1: spi@10070000 {
+                       compatible = "arm,pl022", "arm,primecell";
+                       reg = <0x0 0x10070000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_SPI1_APB>,
+                                <&syscrg JH7110_SYSCLK_SPI1_APB>;
+                       clock-names = "sspclk", "apb_pclk";
+                       resets = <&syscrg JH7110_SYSRST_SPI1_APB>;
+                       interrupts = <39>;
+                       arm,primecell-periphid = <0x00041022>;
+                       num-cs = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               spi2: spi@10080000 {
+                       compatible = "arm,pl022", "arm,primecell";
+                       reg = <0x0 0x10080000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_SPI2_APB>,
+                                <&syscrg JH7110_SYSCLK_SPI2_APB>;
+                       clock-names = "sspclk", "apb_pclk";
+                       resets = <&syscrg JH7110_SYSRST_SPI2_APB>;
+                       interrupts = <40>;
+                       arm,primecell-periphid = <0x00041022>;
+                       num-cs = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
                usb0: usb@10100000 {
                        compatible = "starfive,jh7110-usb";
                        ranges = <0x0 0x0 0x10100000 0x100000>;
@@ -610,6 +655,66 @@
                        status = "disabled";
                };
 
+               spi3: spi@12070000 {
+                       compatible = "arm,pl022", "arm,primecell";
+                       reg = <0x0 0x12070000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_SPI3_APB>,
+                                <&syscrg JH7110_SYSCLK_SPI3_APB>;
+                       clock-names = "sspclk", "apb_pclk";
+                       resets = <&syscrg JH7110_SYSRST_SPI3_APB>;
+                       interrupts = <52>;
+                       arm,primecell-periphid = <0x00041022>;
+                       num-cs = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               spi4: spi@12080000 {
+                       compatible = "arm,pl022", "arm,primecell";
+                       reg = <0x0 0x12080000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_SPI4_APB>,
+                                <&syscrg JH7110_SYSCLK_SPI4_APB>;
+                       clock-names = "sspclk", "apb_pclk";
+                       resets = <&syscrg JH7110_SYSRST_SPI4_APB>;
+                       interrupts = <53>;
+                       arm,primecell-periphid = <0x00041022>;
+                       num-cs = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               spi5: spi@12090000 {
+                       compatible = "arm,pl022", "arm,primecell";
+                       reg = <0x0 0x12090000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_SPI5_APB>,
+                                <&syscrg JH7110_SYSCLK_SPI5_APB>;
+                       clock-names = "sspclk", "apb_pclk";
+                       resets = <&syscrg JH7110_SYSRST_SPI5_APB>;
+                       interrupts = <54>;
+                       arm,primecell-periphid = <0x00041022>;
+                       num-cs = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               spi6: spi@120a0000 {
+                       compatible = "arm,pl022", "arm,primecell";
+                       reg = <0x0 0x120A0000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_SPI6_APB>,
+                                <&syscrg JH7110_SYSCLK_SPI6_APB>;
+                       clock-names = "sspclk", "apb_pclk";
+                       resets = <&syscrg JH7110_SYSRST_SPI6_APB>;
+                       interrupts = <55>;
+                       arm,primecell-periphid = <0x00041022>;
+                       num-cs = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
                sfctemp: temperature-sensor@120e0000 {
                        compatible = "starfive,jh7110-temp";
                        reg = <0x0 0x120e0000 0x0 0x10000>;