drm/amdgpu: correct clock gating settings on feature unsupported

Clock gating setting is still performed even when the corresponding
CG feature is not supported. And the tricky part is disablement is
actually performed no matter for enablement or disablement request.
That seems not logically right.
Considering HW should already properly take care of the CG state, we
will just skip the corresponding clock gating setting when the feature
is not supported.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
index 5b90efd6f6d04721fdf828801cabe5b56792a278..3ac505d954c4622264441f3d91a54dd7ec532faa 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
@@ -36,9 +36,12 @@ athub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 {
        uint32_t def, data;
 
+       if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
+               return;
+
        def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
 
-       if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
+       if (enable)
                data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
        else
                data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
@@ -53,10 +56,13 @@ athub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 {
        uint32_t def, data;
 
+       if (!((adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
+              (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)))
+               return;
+
        def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
 
-       if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
-           (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
+       if (enable)
                data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
        else
                data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index d08a823827a399a09e2cdee127343dfe20f95ecd..c19436570f42332dc0de7a8e6bf4df918696044f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7777,8 +7777,11 @@ static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade
 {
        uint32_t data, def;
 
+       if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG))
+               return;
+
        /* It is disabled by HW by default */
-       if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
+       if (enable) {
                /* 0 - Disable some blocks' MGCG */
                WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
                WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
@@ -7845,22 +7848,34 @@ static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
 {
        uint32_t data, def;
 
+       if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)))
+               return;
+
        /* Enable 3D CGCG/CGLS */
-       if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
+       if (enable) {
                /* write cmd to clear cgcg/cgls ov */
                def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
+
                /* unset CGCG override */
-               data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
+               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
+                       data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
+
                /* update CGCG and CGLS override bits */
                if (def != data)
                        WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
+
                /* enable 3Dcgcg FSM(0x0000363f) */
                def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
-               data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
-                       RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
+               data = 0;
+
+               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
+                       data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
+                               RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
+
                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
                        data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
                                RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
+
                if (def != data)
                        WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
 
@@ -7873,9 +7888,14 @@ static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
        } else {
                /* Disable CGCG/CGLS */
                def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
+
                /* disable cgcg, cgls should be disabled */
-               data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
-                         RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
+               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
+                       data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
+
+               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
+                       data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
+
                /* disable cgcg and cgls in FSM */
                if (def != data)
                        WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
@@ -7887,25 +7907,35 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
 {
        uint32_t def, data;
 
-       if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
+       if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)))
+               return;
+
+       if (enable) {
                def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
+
                /* unset CGCG override */
-               data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
+               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
+                       data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
+
                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
                        data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
-               else
-                       data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
+
                /* update CGCG and CGLS override bits */
                if (def != data)
                        WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
 
                /* enable cgcg FSM(0x0000363F) */
                def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
-               data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
-                       RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
+               data = 0;
+
+               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
+                       data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
+                               RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
+
                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
                        data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
                                RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
+
                if (def != data)
                        WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
 
@@ -7917,8 +7947,14 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
                        WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
        } else {
                def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
+
                /* reset CGCG/CGLS bits */
-               data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
+               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
+                       data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
+
+               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
+                       data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
+
                /* disable cgcg and cgls in FSM */
                if (def != data)
                        WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
@@ -7930,7 +7966,10 @@ static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
 {
        uint32_t def, data;
 
-       if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) {
+       if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
+               return;
+
+       if (enable) {
                def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
                /* unset FGCG override */
                data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index f7e93bbc4e157f963bff92c10dc22a116ca92ec9..7ded6b2f058ef0a21b3fdf0d038c9fb5474fc9db 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -568,6 +568,9 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
 {
        uint32_t def, data, def1, data1;
 
+       if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
+               return;
+
        switch (adev->asic_type) {
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
@@ -582,7 +585,7 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
                break;
        }
 
-       if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
+       if (enable) {
                data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;
 
                data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
@@ -627,6 +630,9 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
 {
        uint32_t def, data;
 
+       if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
+               return;
+
        switch (adev->asic_type) {
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
@@ -639,7 +645,7 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
                break;
        }
 
-       if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
+       if (enable)
                data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
        else
                data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
index 754b11dea6f0421bdf586569bc71c5fff093ca18..7b79eeaa88aa65fee7002a8b9cb56a218e3e3709 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
@@ -220,8 +220,11 @@ static void nbio_v2_3_update_medium_grain_clock_gating(struct amdgpu_device *ade
 {
        uint32_t def, data;
 
+       if (!(adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
+               return;
+
        def = data = RREG32_PCIE(smnCPM_CONTROL);
-       if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) {
+       if (enable) {
                data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
                         CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
                         CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
@@ -246,8 +249,11 @@ static void nbio_v2_3_update_medium_grain_light_sleep(struct amdgpu_device *adev
 {
        uint32_t def, data;
 
+       if (!(adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
+               return;
+
        def = data = RREG32_PCIE(smnPCIE_CNTL2);
-       if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
+       if (enable) {
                data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
                         PCIE_CNTL2__MST_MEM_LS_EN_MASK |
                         PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);

diff --git a/drivers/gpu/drm/amd/amdgpu/smuio_v11_0.c b/drivers/gpu/drm/amd/amdgpu/smuio_v11_0.c
index e9c474c217ec02d087589d28d320b82869d9894b..b6f1322f908cb66fcc1a40795338ea192444d3ae 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/smuio_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/smuio_v11_0.c
@@ -43,9 +43,12 @@ static void smuio_v11_0_update_rom_clock_gating(struct amdgpu_device *adev, bool
        if (adev->flags & AMD_IS_APU)
                return;
 
+       if (!(adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
+               return;
+
        def = data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);
 
-       if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
+       if (enable)
                data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
                        CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
        else