soc: sifive: ccache: fix missing free_irq() in error path in sifive_ccache_init()

Add missing free_irq() before return error from sifive_ccache_init().

Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
index 25019c16d8ae9b8aaafe5c75c7eb55e03d8b0c4c..98269d056728cd2d7166b754927ea2817e30b017 100644 (file)
--- a/drivers/soc/sifive/sifive_ccache.c
+++ b/drivers/soc/sifive/sifive_ccache.c
@@ -240,7 +240,7 @@ static int __init sifive_ccache_init(void)
                                 NULL);
                if (rc) {
                        pr_err("Could not request IRQ %d\n", g_irq[i]);
-                       goto err_unmap;
+                       goto err_free_irq;
                }
        }
 
@@ -254,6 +254,9 @@ static int __init sifive_ccache_init(void)
 #endif
        return 0;
 
+err_free_irq:
+       while (--i >= 0)
+               free_irq(g_irq[i], NULL);
 err_unmap:
        iounmap(ccache_base);
        return rc;