arm64: dts: qcom: sm8550: add UART14 nodes

Add the Geni High Speed UART QUP instance 2 element 6
node and associated default pinctrl.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230911-topic-sm8550-upstream-bt-v4-1-a5a428c77418@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index d115960bdeec8a7edd3dd00a30a388147588c421..4109ca9188d17423273721f594d89b889ec68310 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1054,6 +1054,20 @@
                                status = "disabled";
                        };
 
+                       uart14: serial@898000 {
+                               compatible = "qcom,geni-uart";
+                               reg = <0 0x898000 0 0x4000>;
+                               clock-names = "se";
+                               clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
+                               interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
+                               interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+                                               <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
+                               interconnect-names = "qup-core", "qup-config";
+                               status = "disabled";
+                       };
+
                        i2c15: i2c@89c000 {
                                compatible = "qcom,geni-i2c";
                                reg = <0 0x0089c000 0 0x4000>;
@@ -3498,6 +3512,22 @@
                                bias-disable;
                        };
 
+                       qup_uart14_default: qup-uart14-default-state {
+                               /* TX, RX */
+                               pins = "gpio78", "gpio79";
+                               function = "qup2_se6";
+                               drive-strength = <2>;
+                               bias-pull-up;
+                       };
+
+                       qup_uart14_cts_rts: qup-uart14-cts-rts-state {
+                               /* CTS, RTS */
+                               pins = "gpio76", "gpio77";
+                               function = "qup2_se6";
+                               drive-strength = <2>;
+                               bias-pull-down;
+                       };
+
                        sdc2_sleep: sdc2-sleep-state {
                                clk-pins {
                                        pins = "sdc2_clk";