clk: renesas: r8a779f0: Add SDHI0 clock

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220603233437.21819-1-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
index 0aec5e8ffd964d6a63d07ed643dd8a0f20afef7a..e6f41b9f765a1abd457071bda5a170d5142485c8 100644 (file)
--- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
@@ -128,6 +128,7 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
        DEF_MOD("scif1",        703,    R8A779F0_CLK_S0D12_PER),
        DEF_MOD("scif3",        704,    R8A779F0_CLK_S0D12_PER),
        DEF_MOD("scif4",        705,    R8A779F0_CLK_S0D12_PER),
+       DEF_MOD("sdhi0",        706,    R8A779F0_CLK_SD0),
        DEF_MOD("sys-dmac0",    709,    R8A779F0_CLK_S0D3_PER),
        DEF_MOD("sys-dmac1",    710,    R8A779F0_CLK_S0D3_PER),
        DEF_MOD("wdt",          907,    R8A779F0_CLK_R),