wifi: rtlwifi: rtl8821ae: Reverse PM Capability exists check

Check if PM Capability does not exists and return early which follows
the usual error handling pattern.

Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20231124084725.12738-6-ilpo.jarvinen@linux.intel.com

diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c
index 6ae37d61a2a2164a588d926c7d2a57aa618def08..53cfeed0b03094d33b590f9951ddccdaf1614749 100644 (file)
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c
@@ -2305,30 +2305,31 @@ static void _rtl8821ae_clear_pci_pme_status(struct ieee80211_hw *hw)
                }
        } while (cnt++ < 200);
 
-       if (cap_id == 0x01) {
-               /* Get the PM CSR (Control/Status Register),
-                * The PME_Status is located at PM Capatibility offset 5, bit 7
-                */
-               pci_read_config_byte(rtlpci->pdev, cap_pointer + 5, &pmcs_reg);
-
-               if (pmcs_reg & BIT(7)) {
-                       /* Clear PME_Status with write */
-                       pci_write_config_byte(rtlpci->pdev, cap_pointer + 5,
-                                             pmcs_reg);
-                       /* Read it back to check */
-                       pci_read_config_byte(rtlpci->pdev, cap_pointer + 5,
-                                            &pmcs_reg);
-                       rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
-                               "Clear PME status 0x%2x to 0x%2x\n",
-                               cap_pointer + 5, pmcs_reg);
-               } else {
-                       rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
-                               "PME status(0x%2x) = 0x%2x\n",
-                               cap_pointer + 5, pmcs_reg);
-               }
-       } else {
+       if (cap_id != 0x01) {
                rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING,
                        "Cannot find PME Capability\n");
+               return;
+       }
+
+       /* Get the PM CSR (Control/Status Register),
+        * The PME_Status is located at PM Capatibility offset 5, bit 7
+        */
+       pci_read_config_byte(rtlpci->pdev, cap_pointer + 5, &pmcs_reg);
+
+       if (pmcs_reg & BIT(7)) {
+               /* Clear PME_Status with write */
+               pci_write_config_byte(rtlpci->pdev, cap_pointer + 5,
+                                     pmcs_reg);
+               /* Read it back to check */
+               pci_read_config_byte(rtlpci->pdev, cap_pointer + 5,
+                                    &pmcs_reg);
+               rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
+                       "Clear PME status 0x%2x to 0x%2x\n",
+                       cap_pointer + 5, pmcs_reg);
+       } else {
+               rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
+                       "PME status(0x%2x) = 0x%2x\n",
+                       cap_pointer + 5, pmcs_reg);
        }
 }