drm/msm/dpu: create a dpu_hw_clk_force_ctrl() helper

Add an helper to setup the force clock control as it will
be used in multiple HW files.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/562323/
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
index cff48763ce25e46f7dc759ee2e6e12afd2578ab0..24e734768a727663bb16184aadd1f130dbbb82c0 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
@@ -66,34 +66,13 @@ static void dpu_hw_setup_split_pipe(struct dpu_hw_mdp *mdp,
 static bool dpu_hw_setup_clk_force_ctrl(struct dpu_hw_mdp *mdp,
                enum dpu_clk_ctrl_type clk_ctrl, bool enable)
 {
-       struct dpu_hw_blk_reg_map *c;
-       u32 reg_off, bit_off;
-       u32 reg_val, new_val;
-       bool clk_forced_on;
-
        if (!mdp)
                return false;
 
-       c = &mdp->hw;
-
        if (clk_ctrl <= DPU_CLK_CTRL_NONE || clk_ctrl >= DPU_CLK_CTRL_MAX)
                return false;
 
-       reg_off = mdp->caps->clk_ctrls[clk_ctrl].reg_off;
-       bit_off = mdp->caps->clk_ctrls[clk_ctrl].bit_off;
-
-       reg_val = DPU_REG_READ(c, reg_off);
-
-       if (enable)
-               new_val = reg_val | BIT(bit_off);
-       else
-               new_val = reg_val & ~BIT(bit_off);
-
-       DPU_REG_WRITE(c, reg_off, new_val);
-
-       clk_forced_on = !(reg_val & BIT(bit_off));
-
-       return clk_forced_on;
+       return dpu_hw_clk_force_ctrl(&mdp->hw, &mdp->caps->clk_ctrls[clk_ctrl], enable);
 }
 
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
index 9d2273fd2fed58e5a58965d78958bfea49272b8d..18b16b2d2bf52ff791a313272ce91424553acda5 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
@@ -546,3 +546,24 @@ void dpu_setup_cdp(struct dpu_hw_blk_reg_map *c, u32 offset,
 
        DPU_REG_WRITE(c, offset, cdp_cntl);
 }
+
+bool dpu_hw_clk_force_ctrl(struct dpu_hw_blk_reg_map *c,
+                          const struct dpu_clk_ctrl_reg *clk_ctrl_reg,
+                          bool enable)
+{
+       u32 reg_val, new_val;
+       bool clk_forced_on;
+
+       reg_val = DPU_REG_READ(c, clk_ctrl_reg->reg_off);
+
+       if (enable)
+               new_val = reg_val | BIT(clk_ctrl_reg->bit_off);
+       else
+               new_val = reg_val & ~BIT(clk_ctrl_reg->bit_off);
+
+       DPU_REG_WRITE(c, clk_ctrl_reg->reg_off, new_val);
+
+       clk_forced_on = !(reg_val & BIT(clk_ctrl_reg->bit_off));
+
+       return clk_forced_on;
+}

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index 1f6079f47071095774cd75d826038a93b57cac6c..4bea139081bcd6c726bf29c7cd303627b5917ce3 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -367,4 +367,8 @@ int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,
                u32 misr_signature_offset,
                u32 *misr_value);
 
+bool dpu_hw_clk_force_ctrl(struct dpu_hw_blk_reg_map *c,
+                          const struct dpu_clk_ctrl_reg *clk_ctrl_reg,
+                          bool enable);
+
 #endif /* _DPU_HW_UTIL_H */