clk: mediatek: reset: Add new register reset function with device
authorRex-BC Chen <rex-bc.chen@mediatek.com>
Mon, 23 May 2022 09:33:37 +0000 (17:33 +0800)
committerStephen Boyd <sboyd@kernel.org>
Thu, 16 Jun 2022 00:24:13 +0000 (17:24 -0700)
Using device to register reset controller is a better implementation in
current drivers. Howerver, some clock drviers of MediaTek only provide
device_node.

Therefore, we still remain the register reset function with device_node
and add a new function with device to register reset controller.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: NĂ­colas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: NĂ­colas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220523093346.28493-11-rex-bc.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
13 files changed:
drivers/clk/mediatek/clk-mt2701-eth.c
drivers/clk/mediatek/clk-mt2701-g3d.c
drivers/clk/mediatek/clk-mt2701-hif.c
drivers/clk/mediatek/clk-mt2701.c
drivers/clk/mediatek/clk-mt2712.c
drivers/clk/mediatek/clk-mt7622-eth.c
drivers/clk/mediatek/clk-mt7622-hif.c
drivers/clk/mediatek/clk-mt7622.c
drivers/clk/mediatek/clk-mt7629-eth.c
drivers/clk/mediatek/clk-mt7629-hif.c
drivers/clk/mediatek/clk-mt8183.c
drivers/clk/mediatek/reset.c
drivers/clk/mediatek/reset.h

index b4e7f38860d0c33b7df52c16442e33551d1cd48b..edf1e2ed2b596ec3921ca593cd6b0e388777a096 100644 (file)
@@ -66,7 +66,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev)
                        "could not register clock provider: %s: %d\n",
                        pdev->name, r);
 
-       mtk_register_reset_controller(node, &clk_rst_desc);
+       mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
        return r;
 }
index 1431fa76a0f8510f78bb783e19e8def2f4c0d0c0..1458109d99d947dde4327f0b7c5f03327367e2b6 100644 (file)
@@ -60,7 +60,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
                        "could not register clock provider: %s: %d\n",
                        pdev->name, r);
 
-       mtk_register_reset_controller(node, &clk_rst_desc);
+       mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
        return r;
 }
index 60bda56a102cccbb124dad9c4e313d500b47e795..434cbbe8c03713da888ebf90788dcaae731b09f6 100644 (file)
@@ -65,7 +65,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev)
                return r;
        }
 
-       mtk_register_reset_controller(node, &clk_rst_desc);
+       mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
        return 0;
 }
index 6c7a80fb43491946cbb0913d35179dab68a4e9aa..9b442af37e6726b96ab25f73a3ca38f2aff37cd9 100644 (file)
@@ -805,7 +805,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
        if (r)
                return r;
 
-       mtk_register_reset_controller(node, &clk_rst_desc[0]);
+       mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
 
        return 0;
 }
@@ -928,7 +928,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
        if (r)
                return r;
 
-       mtk_register_reset_controller(node, &clk_rst_desc[1]);
+       mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
 
        return 0;
 }
index fd310c375fdf26eae969bb1544ed64dd0227d843..56980dd6c2eafcf97fe6526225f926035d53aa3d 100644 (file)
@@ -1379,7 +1379,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev)
                pr_err("%s(): could not register clock provider: %d\n",
                        __func__, r);
 
-       mtk_register_reset_controller(node, &clk_rst_desc[0]);
+       mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
 
        return r;
 }
@@ -1401,7 +1401,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev)
                pr_err("%s(): could not register clock provider: %d\n",
                        __func__, r);
 
-       mtk_register_reset_controller(node, &clk_rst_desc[1]);
+       mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
 
        return r;
 }
index 90d55f88221545ee3aba7c70cca4430dd1ece578..43de0477d5d998a3704341492e508d3e3ddfe916 100644 (file)
@@ -90,7 +90,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev)
                        "could not register clock provider: %s: %d\n",
                        pdev->name, r);
 
-       mtk_register_reset_controller(node, &clk_rst_desc);
+       mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
        return r;
 }
index 489b64725b22d353514024ac0a7c6fc83832c253..67e96231dd25b865819e31e4c281d1f7e4f78283 100644 (file)
@@ -101,7 +101,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
                        "could not register clock provider: %s: %d\n",
                        pdev->name, r);
 
-       mtk_register_reset_controller(node, &clk_rst_desc);
+       mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
        return r;
 }
@@ -123,7 +123,7 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev)
                        "could not register clock provider: %s: %d\n",
                        pdev->name, r);
 
-       mtk_register_reset_controller(node, &clk_rst_desc);
+       mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
        return r;
 }
index 0cba74d384996085f7d05e9553fd1e0b03b65ade..3b55f8641fae0cd5b2c54fdea876445819a97db7 100644 (file)
@@ -681,7 +681,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
        if (r)
                return r;
 
-       mtk_register_reset_controller(node, &clk_rst_desc[0]);
+       mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
 
        return 0;
 }
@@ -732,7 +732,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
 
        clk_prepare_enable(clk_data->hws[CLK_PERI_UART0_PD]->clk);
 
-       mtk_register_reset_controller(node, &clk_rst_desc[1]);
+       mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
 
        return 0;
 }
index 11b346c9d916d66aed4fc9d1b1f5ebfe1d440c4f..282dd6559465424b23ecead143ca1066f736e220 100644 (file)
@@ -100,7 +100,7 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev)
                        "could not register clock provider: %s: %d\n",
                        pdev->name, r);
 
-       mtk_register_reset_controller(node, &clk_rst_desc);
+       mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
        return r;
 }
index c0583043710fd9e5c4e07dd94ef5bba31cf23f99..0c8b9e1397890a334d681ba108aa0089a8e097d6 100644 (file)
@@ -96,7 +96,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
                        "could not register clock provider: %s: %d\n",
                        pdev->name, r);
 
-       mtk_register_reset_controller(node, &clk_rst_desc);
+       mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
        return r;
 }
@@ -118,7 +118,7 @@ static int clk_mt7629_pciesys_init(struct platform_device *pdev)
                        "could not register clock provider: %s: %d\n",
                        pdev->name, r);
 
-       mtk_register_reset_controller(node, &clk_rst_desc);
+       mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
        return r;
 }
index 5bc738f4d0e76d50221b0fe23178b676befe6310..b1d810f85b719945fee1132fb56929288a3b22eb 100644 (file)
@@ -1256,7 +1256,7 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev)
                return r;
        }
 
-       mtk_register_reset_controller(node, &clk_rst_desc);
+       mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
 
        return r;
 }
index b9718f0f9d167b659ff6db7ac158267fbafb5e0b..179505549a7c4d6f7e4d1b90c117c1e6dc8cc6d6 100644 (file)
@@ -169,4 +169,64 @@ int mtk_register_reset_controller(struct device_node *np,
        return 0;
 }
 
+int mtk_register_reset_controller_with_dev(struct device *dev,
+                                          const struct mtk_clk_rst_desc *desc)
+{
+       struct device_node *np = dev->of_node;
+       struct regmap *regmap;
+       const struct reset_control_ops *rcops = NULL;
+       struct mtk_clk_rst_data *data;
+       int ret;
+
+       if (!desc) {
+               dev_err(dev, "mtk clock reset desc is NULL\n");
+               return -EINVAL;
+       }
+
+       switch (desc->version) {
+       case MTK_RST_SIMPLE:
+               rcops = &mtk_reset_ops;
+               break;
+       case MTK_RST_SET_CLR:
+               rcops = &mtk_reset_ops_set_clr;
+               break;
+       default:
+               dev_err(dev, "Unknown reset version %d\n", desc->version);
+               return -EINVAL;
+       }
+
+       regmap = device_node_to_regmap(np);
+       if (IS_ERR(regmap)) {
+               dev_err(dev, "Cannot find regmap %pe\n", regmap);
+               return -EINVAL;
+       }
+
+       data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+       if (!data)
+               return -ENOMEM;
+
+       data->desc = desc;
+       data->regmap = regmap;
+       data->rcdev.owner = THIS_MODULE;
+       data->rcdev.ops = rcops;
+       data->rcdev.of_node = np;
+       data->rcdev.dev = dev;
+
+       if (data->desc->rst_idx_map_nr > 0) {
+               data->rcdev.of_reset_n_cells = 1;
+               data->rcdev.nr_resets = desc->rst_idx_map_nr;
+               data->rcdev.of_xlate = reset_xlate;
+       } else {
+               data->rcdev.nr_resets = desc->rst_bank_nr * RST_NR_PER_BANK;
+       }
+
+       ret = devm_reset_controller_register(dev, &data->rcdev);
+       if (ret) {
+               dev_err(dev, "could not register reset controller: %d\n", ret);
+               return ret;
+       }
+
+       return 0;
+}
+
 MODULE_LICENSE("GPL");
index 260f25f2765693732db3263318923ea78b876331..f7e1f31e394626b47dbe621ff63058a653151eae 100644 (file)
@@ -62,4 +62,14 @@ struct mtk_clk_rst_data {
 int mtk_register_reset_controller(struct device_node *np,
                                  const struct mtk_clk_rst_desc *desc);
 
+/**
+ * mtk_register_reset_controller - Register mediatek clock reset controller with device
+ * @np: Pointer to device.
+ * @desc: Constant pointer to description of clock reset.
+ *
+ * Return: 0 on success and errorno otherwise.
+ */
+int mtk_register_reset_controller_with_dev(struct device *dev,
+                                          const struct mtk_clk_rst_desc *desc);
+
 #endif /* __DRV_CLK_MTK_RESET_H */