drm/amd/display: Update bouding box values for DCN32

All clock values came from firmware, but bounding box values can be
helpful in some debug situations. This commit updates some of the values
associated with clock speed and memory channels.

Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 4548320217fc588c3dee8a57c46906e72517c318..f0037cb43dca9f54124c3f49fd18732e359b7e28 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -109,7 +109,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
                {
                        .state = 0,
                        .dcfclk_mhz = 1564.0,
-                       .fabricclk_mhz = 400.0,
+                       .fabricclk_mhz = 2500.0,
                        .dispclk_mhz = 2150.0,
                        .dppclk_mhz = 2150.0,
                        .phyclk_mhz = 810.0,
@@ -117,7 +117,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
                        .phyclk_d32_mhz = 625.0,
                        .socclk_mhz = 1200.0,
                        .dscclk_mhz = 716.667,
-                       .dram_speed_mts = 16000.0,
+                       .dram_speed_mts = 18000.0,
                        .dtbclk_mhz = 1564.0,
                },
        },
@@ -148,7 +148,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
        .max_avg_fabric_bw_use_normal_percent = 60.0,
        .max_avg_dram_bw_use_normal_strobe_percent = 50.0,
        .max_avg_dram_bw_use_normal_percent = 15.0,
-       .num_chans = 8,
+       .num_chans = 24,
        .dram_channel_width_bytes = 2,
        .fabric_datapath_to_dcn_data_return_bytes = 64,
        .return_bus_width_bytes = 64,