arm64: dts: realtek: Add RTD1395 and BPi-M4

Add Device Trees for Realtek RTD1395 SoC and Banana Pi BPi-M4 SBC.

For now reuse RTD1295 reset constants.

Signed-off-by: Andreas Färber <afaerber@suse.de>

diff --git a/arch/arm64/boot/dts/realtek/Makefile b/arch/arm64/boot/dts/realtek/Makefile
index 555638ada721988615ded572453d41d7dca23848..edc85ee8c4bf897d67025ea98b286ec282af48d6 100644 (file)
--- a/arch/arm64/boot/dts/realtek/Makefile
+++ b/arch/arm64/boot/dts/realtek/Makefile
@@ -7,3 +7,5 @@ dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-probox2-ava.dtb
 dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb
 
 dtb-$(CONFIG_ARCH_REALTEK) += rtd1296-ds418.dtb
+
+dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-bpi-m4.dtb

diff --git a/arch/arm64/boot/dts/realtek/rtd1395-bpi-m4.dts b/arch/arm64/boot/dts/realtek/rtd1395-bpi-m4.dts
new file mode 100644 (file)
index 0000000..9891967
--- /dev/null
+++ b/arch/arm64/boot/dts/realtek/rtd1395-bpi-m4.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+/*
+ * Copyright (c) 2019 Andreas Färber
+ */
+
+/dts-v1/;
+
+#include "rtd1395.dtsi"
+
+/ {
+       compatible = "bananapi,bpi-m4", "realtek,rtd1395";
+       model = "Banana Pi BPI-M4";
+
+       memory@2f000 {
+               device_type = "memory";
+               reg = <0x2f000 0x3ffd1000>; /* boot ROM to 1 GiB or 2 GiB */
+       };
+
+       aliases {
+               serial0 = &uart0;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+};
+
+&uart0 {
+       status = "okay";
+};

diff --git a/arch/arm64/boot/dts/realtek/rtd1395.dtsi b/arch/arm64/boot/dts/realtek/rtd1395.dtsi
new file mode 100644 (file)
index 0000000..05c9216
--- /dev/null
+++ b/arch/arm64/boot/dts/realtek/rtd1395.dtsi
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+/*
+ * Realtek RTD1395 SoC
+ *
+ * Copyright (c) 2019 Andreas Färber
+ */
+
+#include "rtd139x.dtsi"
+
+/ {
+       compatible = "realtek,rtd1395";
+
+       cpus {
+               #address-cells = <2>;
+               #size-cells = <0>;
+
+               cpu0: cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53";
+                       reg = <0x0 0x0>;
+                       next-level-cache = <&l2>;
+               };
+
+               cpu1: cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53";
+                       reg = <0x0 0x1>;
+                       next-level-cache = <&l2>;
+               };
+
+               cpu2: cpu@2 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53";
+                       reg = <0x0 0x2>;
+                       next-level-cache = <&l2>;
+               };
+
+               cpu3: cpu@3 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53";
+                       reg = <0x0 0x3>;
+                       next-level-cache = <&l2>;
+               };
+
+               l2: l2-cache {
+                       compatible = "cache";
+               };
+       };
+
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupts = <GIC_PPI 13
+                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 14
+                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 11
+                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 10
+                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+       };
+};
+
+&arm_pmu {
+       interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+};

diff --git a/arch/arm64/boot/dts/realtek/rtd139x.dtsi b/arch/arm64/boot/dts/realtek/rtd139x.dtsi
new file mode 100644 (file)
index 0000000..c11a505
--- /dev/null
+++ b/arch/arm64/boot/dts/realtek/rtd139x.dtsi
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+/*
+ * Realtek RTD1395 SoC family
+ *
+ * Copyright (c) 2019 Andreas Färber
+ */
+
+/memreserve/   0x0000000000000000 0x000000000002f000;
+/memreserve/   0x000000000002f000 0x00000000000d1000;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/realtek,rtd1295.h>
+
+/ {
+       interrupt-parent = <&gic>;
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       reserved-memory {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               rpc_comm: rpc@2f000 {
+                       reg = <0x2f000 0x1000>;
+               };
+
+               rpc_ringbuf: rpc@1ffe000 {
+                       reg = <0x1ffe000 0x4000>;
+               };
+
+               tee: tee@10100000 {
+                       reg = <0x10100000 0xf00000>;
+                       no-map;
+               };
+       };
+
+       arm_pmu: arm-pmu {
+               compatible = "arm,cortex-a53-pmu";
+               interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+       };
+
+       osc27M: osc {
+               compatible = "fixed-clock";
+               clock-frequency = <27000000>;
+               #clock-cells = <0>;
+               clock-output-names = "osc27M";
+       };
+
+       soc {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */
+                        <0x98000000 0x98000000 0x68000000>;
+
+               rbus: bus@98000000 {
+                       compatible = "simple-bus";
+                       reg = <0x98000000 0x200000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x98000000 0x200000>;
+
+                       reset1: reset-controller@0 {
+                               compatible = "snps,dw-low-reset";
+                               reg = <0x0 0x4>;
+                               #reset-cells = <1>;
+                       };
+
+                       reset2: reset-controller@4 {
+                               compatible = "snps,dw-low-reset";
+                               reg = <0x4 0x4>;
+                               #reset-cells = <1>;
+                       };
+
+                       reset3: reset-controller@8 {
+                               compatible = "snps,dw-low-reset";
+                               reg = <0x8 0x4>;
+                               #reset-cells = <1>;
+                       };
+
+                       reset4: reset-controller@50 {
+                               compatible = "snps,dw-low-reset";
+                               reg = <0x50 0x4>;
+                               #reset-cells = <1>;
+                       };
+
+                       iso_reset: reset-controller@7088 {
+                               compatible = "snps,dw-low-reset";
+                               reg = <0x7088 0x4>;
+                               #reset-cells = <1>;
+                       };
+
+                       wdt: watchdog@7680 {
+                               compatible = "realtek,rtd1295-watchdog";
+                               reg = <0x7680 0x100>;
+                               clocks = <&osc27M>;
+                       };
+
+                       uart0: serial@7800 {
+                               compatible = "snps,dw-apb-uart";
+                               reg = <0x7800 0x400>;
+                               reg-shift = <2>;
+                               reg-io-width = <4>;
+                               clock-frequency = <27000000>;
+                               resets = <&iso_reset RTD1295_ISO_RSTN_UR0>;
+                               status = "disabled";
+                       };
+
+                       uart1: serial@1b200 {
+                               compatible = "snps,dw-apb-uart";
+                               reg = <0x1b200 0x100>;
+                               reg-shift = <2>;
+                               reg-io-width = <4>;
+                               clock-frequency = <432000000>;
+                               resets = <&reset2 RTD1295_RSTN_UR1>;
+                               status = "disabled";
+                       };
+
+                       uart2: serial@1b400 {
+                               compatible = "snps,dw-apb-uart";
+                               reg = <0x1b400 0x100>;
+                               reg-shift = <2>;
+                               reg-io-width = <4>;
+                               clock-frequency = <432000000>;
+                               resets = <&reset2 RTD1295_RSTN_UR2>;
+                               status = "disabled";
+                       };
+               };
+
+               gic: interrupt-controller@ff011000 {
+                       compatible = "arm,gic-400";
+                       reg = <0xff011000 0x1000>,
+                             <0xff012000 0x2000>,
+                             <0xff014000 0x2000>,
+                             <0xff016000 0x2000>;
+                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+                       interrupt-controller;
+                       #interrupt-cells = <3>;
+               };
+       };
+};