PCI: qcom: Sort and group registers and bitfield definitions

Sorting the registers and their bit definitions will make it easier to add
more definitions in the future and it also helps in maintenance.

While at it, let's also group the registers and bit definitions separately
as done in the pcie-qcom-ep driver.

Link: https://lore.kernel.org/r/20230316081117.14288-4-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 5855ad8e9c1cfabe2ad6b8ef18a9cfb6bd6b3641..a33653d576b621896d9d207c2a3d59ecb809e6f9 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -33,7 +33,36 @@
 #include "../../pci.h"
 #include "pcie-designware.h"
 
+/* PARF registers */
 #define PARF_SYS_CTRL                          0x00
+#define PARF_PM_CTRL                           0x20
+#define PARF_PCS_DEEMPH                                0x34
+#define PARF_PCS_SWING                         0x38
+#define PARF_PHY_CTRL                          0x40
+#define PARF_PHY_REFCLK                                0x4C
+#define PARF_CONFIG_BITS                       0x50
+#define PARF_DBI_BASE_ADDR                     0x168
+#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3         0x16C /* Register offset specific to IP ver 2.3.3 */
+#define PARF_MHI_CLOCK_RESET_CTRL              0x174
+#define PARF_AXI_MSTR_WR_ADDR_HALT             0x178
+#define PARF_AXI_MSTR_WR_ADDR_HALT_V2          0x1A8
+#define PARF_Q2A_FLUSH                         0x1AC
+#define PARF_LTSSM                             0x1B0
+#define PARF_SID_OFFSET                                0x234
+#define PARF_BDF_TRANSLATE_CFG                 0x24C
+#define PARF_SLV_ADDR_SPACE_SIZE               0x358
+#define PARF_DEVICE_TYPE                       0x1000
+#define PARF_BDF_TO_SID_TABLE_N                        0x2000
+
+/* ELBI registers */
+#define ELBI_SYS_CTRL                          0x04
+
+/* DBI registers */
+#define AXI_MSTR_RESP_COMP_CTRL0               0x818
+#define AXI_MSTR_RESP_COMP_CTRL1               0x81c
+#define MISC_CONTROL_1_REG                     0x8BC
+
+/* PARF_SYS_CTRL register fields */
 #define MST_WAKEUP_EN                          BIT(13)
 #define SLV_WAKEUP_EN                          BIT(12)
 #define MSTR_ACLK_CGC_DIS                      BIT(10)
@@ -43,45 +72,56 @@
 #define L23_CLK_RMV_DIS                                BIT(2)
 #define L1_CLK_RMV_DIS                         BIT(1)
 
-#define PARF_PM_CTRL                           0x20
+/* PARF_PM_CTRL register fields */
 #define REQ_NOT_ENTR_L1                                BIT(5)
 
-#define PARF_PHY_CTRL                          0x40
+/* PARF_PCS_DEEMPH register fields */
+#define PCS_DEEMPH_TX_DEEMPH_GEN1(x)           ((x) << 16)
+#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x)     ((x) << 8)
+#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x)       ((x) << 0)
+
+/* PARF_PCS_SWING register fields */
+#define PCS_SWING_TX_SWING_FULL(x)             ((x) << 8)
+#define PCS_SWING_TX_SWING_LOW(x)              ((x) << 0)
+
+/* PARF_PHY_CTRL register fields */
 #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK      GENMASK(20, 16)
 #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x)                ((x) << 16)
 
-#define PARF_PHY_REFCLK                                0x4C
+/* PARF_PHY_REFCLK register fields */
 #define PHY_REFCLK_SSP_EN                      BIT(16)
 #define PHY_REFCLK_USE_PAD                     BIT(12)
 
-#define PARF_DBI_BASE_ADDR                     0x168
-#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3         0x16C /* Register offset specific to IP rev 2.3.3 */
-#define PARF_MHI_CLOCK_RESET_CTRL              0x174
+/* PARF_CONFIG_BITS register fields */
+#define PHY_RX0_EQ(x)                          ((x) << 24)
+
+/* PARF_SLV_ADDR_SPACE_SIZE register value */
+#define SLV_ADDR_SPACE_SZ                      0x10000000
+
+/* PARF_MHI_CLOCK_RESET_CTRL register fields */
 #define AHB_CLK_EN                             BIT(0)
 #define MSTR_AXI_CLK_EN                                BIT(1)
 #define BYPASS                                 BIT(4)
 
-#define PARF_AXI_MSTR_WR_ADDR_HALT             0x178
-#define PARF_AXI_MSTR_WR_ADDR_HALT_V2          0x1A8
-#define PARF_LTSSM                             0x1B0
-#define PARF_SID_OFFSET                                0x234
-#define PARF_BDF_TRANSLATE_CFG                 0x24C
-#define PARF_DEVICE_TYPE                       0x1000
-#define PARF_BDF_TO_SID_TABLE_N                        0x2000
+/* PARF_DEVICE_TYPE register fields */
+#define DEVICE_TYPE_RC                         0x4
 
-#define ELBI_SYS_CTRL                          0x04
+/* ELBI_SYS_CTRL register fields */
 #define ELBI_SYS_CTRL_LT_ENABLE                        BIT(0)
 
-#define AXI_MSTR_RESP_COMP_CTRL0               0x818
+/* AXI_MSTR_RESP_COMP_CTRL0 register fields */
 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K       0x4
 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K       0x5
-#define AXI_MSTR_RESP_COMP_CTRL1               0x81c
+
+/* AXI_MSTR_RESP_COMP_CTRL1 register fields */
 #define CFG_BRIDGE_SB_INIT                     BIT(0)
 
-#define PCIE_CAP_SLOT_POWER_LIMIT_VAL          FIELD_PREP(PCI_EXP_SLTCAP_SPLV, \
-                                               250)
-#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE                FIELD_PREP(PCI_EXP_SLTCAP_SPLS, \
-                                               1)
+/* MISC_CONTROL_1_REG register fields */
+#define DBI_RO_WR_EN                           1
+
+/* PCI_EXP_SLTCAP register fields */
+#define PCIE_CAP_SLOT_POWER_LIMIT_VAL          FIELD_PREP(PCI_EXP_SLTCAP_SPLV, 250)
+#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE                FIELD_PREP(PCI_EXP_SLTCAP_SPLS, 1)
 #define PCIE_CAP_SLOT_VAL                      (PCI_EXP_SLTCAP_ABP | \
                                                PCI_EXP_SLTCAP_PCP | \
                                                PCI_EXP_SLTCAP_MRLSP | \
@@ -93,34 +133,12 @@
                                                PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
                                                PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
 
-#define PARF_Q2A_FLUSH                         0x1AC
-
-#define MISC_CONTROL_1_REG                     0x8BC
-#define DBI_RO_WR_EN                           1
-
 #define PERST_DELAY_US                         1000
-/* PARF registers */
-#define PARF_PCS_DEEMPH                                0x34
-#define PCS_DEEMPH_TX_DEEMPH_GEN1(x)           ((x) << 16)
-#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x)     ((x) << 8)
-#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x)       ((x) << 0)
-
-#define PARF_PCS_SWING                         0x38
-#define PCS_SWING_TX_SWING_FULL(x)             ((x) << 8)
-#define PCS_SWING_TX_SWING_LOW(x)              ((x) << 0)
-
-#define PARF_CONFIG_BITS                       0x50
-#define PHY_RX0_EQ(x)                          ((x) << 24)
-
-#define PARF_SLV_ADDR_SPACE_SIZE               0x358
-#define SLV_ADDR_SPACE_SZ                      0x10000000
-
-#define DEVICE_TYPE_RC                         0x4
 
-#define QCOM_PCIE_2_1_0_MAX_SUPPLY     3
-#define QCOM_PCIE_2_1_0_MAX_CLOCKS     5
+#define QCOM_PCIE_2_1_0_MAX_SUPPLY             3
+#define QCOM_PCIE_2_1_0_MAX_CLOCKS             5
 
-#define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0))
+#define QCOM_PCIE_CRC8_POLYNOMIAL              (BIT(2) | BIT(1) | BIT(0))
 
 struct qcom_pcie_resources_2_1_0 {
        struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS];