drm/amd/display: Fix underflow for fused display pipes case

[Why]
Depend on res_pool->res_cap->num_timing_generator to query timing
gernerator information, it would case underflow at the fused display
pipes case.
Due to the res_pool->res_cap->num_timing_generator records default
timing generator resource built in driver, not the current chip.

[How]
Some ASICs would be fused display pipes less than the default setting.
In dcnxx_resource_construct function, driver would obatin real timing
generator count and store it into res_pool->timing_generator_count.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Yi-Ling Chen <Yi-Ling.Chen2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index f19015413ce311c1fc1ff0372a70e163db9bbcb8..530a72e3eefe29b9d767c8784e0b6b0b864d89d4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1365,7 +1365,12 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
                uint32_t opp_id_src1 = OPP_ID_INVALID;
 
                // Step 1: To find out which OPTC is running & OPTC DSC is ON
-               for (i = 0; i < dc->res_pool->res_cap->num_timing_generator; i++) {
+               // We can't use res_pool->res_cap->num_timing_generator to check
+               // Because it records display pipes default setting built in driver,
+               // not display pipes of the current chip.
+               // Some ASICs would be fused display pipes less than the default setting.
+               // In dcnxx_resource_construct function, driver would obatin real information.
+               for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
                        uint32_t optc_dsc_state = 0;
                        struct timing_generator *tg = dc->res_pool->timing_generators[i];