clk: renesas: r9a07g044: Drop WDT2 clock and reset entry

WDT CH2 is specifically to check the operation of Cortex-M33 CPU and if
used from CA55 CPU would result in an unexpected behaviour. Hence drop
WDT2 clock and reset entries.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20221009231013.14791-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 12b1a83625cb90cd251570e7a33191c08330b60b..f5550fccb029cad839d88bf0b159188288e5c7ff 100644 (file)
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -182,7 +182,7 @@ static const struct {
 };
 
 static const struct {
-       struct rzg2l_mod_clk common[77];
+       struct rzg2l_mod_clk common[75];
 #ifdef CONFIG_CLK_R9A07G054
        struct rzg2l_mod_clk drp[0];
 #endif
@@ -224,10 +224,6 @@ static const struct {
                                        0x548, 2),
                DEF_MOD("wdt1_clk",     R9A07G044_WDT1_CLK, R9A07G044_OSCCLK,
                                        0x548, 3),
-               DEF_MOD("wdt2_pclk",    R9A07G044_WDT2_PCLK, R9A07G044_CLK_P0,
-                                       0x548, 4),
-               DEF_MOD("wdt2_clk",     R9A07G044_WDT2_CLK, R9A07G044_OSCCLK,
-                                       0x548, 5),
                DEF_MOD("spi_clk2",     R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1,
                                        0x550, 0),
                DEF_MOD("spi_clk",      R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0,
@@ -366,7 +362,6 @@ static struct rzg2l_reset r9a07g044_resets[] = {
        DEF_RST(R9A07G044_POEG_D_RST, 0x844, 3),
        DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),
        DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),
-       DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2),
        DEF_RST(R9A07G044_SPI_RST, 0x850, 0),
        DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0),
        DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),