clk: meson: g12a: add MIPI ISP clocks

Add the MIPI ISP gate, divider and mux used to feed the MIPI CSI ISP
(Image Signal Processor) IP on the Amlogic G12B SoC.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Daniel Scally <dan.scally@ideasonboard.com>
Tested-by: Daniel Scally <dan.scally@ideasonboard.com>
Link: https://lore.kernel.org/r/20231114-topic-amlogic-upstream-isp-clocks-v1-2-223958791501@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index cadd824336ad01ebca3774c7dda631e157db25dc..2658a52a28ac380fc7e496b71e6ab40294292f46 100644 (file)
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -3754,6 +3754,66 @@ static struct clk_regmap g12a_mipi_dsi_pxclk = {
        },
 };
 
+/* MIPI ISP Clocks */
+
+static const struct clk_parent_data g12b_mipi_isp_parent_data[] = {
+       { .fw_name = "xtal", },
+       { .hw = &g12a_gp0_pll.hw },
+       { .hw = &g12a_hifi_pll.hw },
+       { .hw = &g12a_fclk_div2p5.hw },
+       { .hw = &g12a_fclk_div3.hw },
+       { .hw = &g12a_fclk_div4.hw },
+       { .hw = &g12a_fclk_div5.hw },
+       { .hw = &g12a_fclk_div7.hw },
+};
+
+static struct clk_regmap g12b_mipi_isp_sel = {
+       .data = &(struct clk_regmap_mux_data){
+               .offset = HHI_ISP_CLK_CNTL,
+               .mask = 7,
+               .shift = 9,
+       },
+       .hw.init = &(struct clk_init_data){
+               .name = "mipi_isp_sel",
+               .ops = &clk_regmap_mux_ops,
+               .parent_data = g12b_mipi_isp_parent_data,
+               .num_parents = ARRAY_SIZE(g12b_mipi_isp_parent_data),
+       },
+};
+
+static struct clk_regmap g12b_mipi_isp_div = {
+       .data = &(struct clk_regmap_div_data){
+               .offset = HHI_ISP_CLK_CNTL,
+               .shift = 0,
+               .width = 7,
+       },
+       .hw.init = &(struct clk_init_data){
+               .name = "mipi_isp_div",
+               .ops = &clk_regmap_divider_ops,
+               .parent_hws = (const struct clk_hw *[]) {
+                       &g12b_mipi_isp_sel.hw
+               },
+               .num_parents = 1,
+               .flags = CLK_SET_RATE_PARENT,
+       },
+};
+
+static struct clk_regmap g12b_mipi_isp = {
+       .data = &(struct clk_regmap_gate_data){
+               .offset = HHI_ISP_CLK_CNTL,
+               .bit_idx = 8,
+       },
+       .hw.init = &(struct clk_init_data) {
+               .name = "mipi_isp",
+               .ops = &clk_regmap_gate_ops,
+               .parent_hws = (const struct clk_hw *[]) {
+                       &g12b_mipi_isp_div.hw
+               },
+               .num_parents = 1,
+               .flags = CLK_SET_RATE_PARENT,
+       },
+};
+
 /* HDMI Clocks */
 
 static const struct clk_parent_data g12a_hdmi_parent_data[] = {
@@ -4765,6 +4825,9 @@ static struct clk_hw *g12b_hw_clks[] = {
        [CLKID_MIPI_DSI_PXCLK_SEL]      = &g12a_mipi_dsi_pxclk_sel.hw,
        [CLKID_MIPI_DSI_PXCLK_DIV]      = &g12a_mipi_dsi_pxclk_div.hw,
        [CLKID_MIPI_DSI_PXCLK]          = &g12a_mipi_dsi_pxclk.hw,
+       [CLKID_MIPI_ISP_SEL]            = &g12b_mipi_isp_sel.hw,
+       [CLKID_MIPI_ISP_DIV]            = &g12b_mipi_isp_div.hw,
+       [CLKID_MIPI_ISP]                = &g12b_mipi_isp.hw,
 };
 
 static struct clk_hw *sm1_hw_clks[] = {
@@ -5261,6 +5324,9 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
        &g12a_mipi_dsi_pxclk_sel,
        &g12a_mipi_dsi_pxclk_div,
        &g12a_mipi_dsi_pxclk,
+       &g12b_mipi_isp_sel,
+       &g12b_mipi_isp_div,
+       &g12b_mipi_isp,
 };
 
 static const struct reg_sequence g12a_init_regs[] = {

diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
index f11ee3c598497c8c8fbb1114c597bfbc0c175160..27df99c4565aed5036be1fb106ee096a0a1127b5 100644 (file)
--- a/drivers/clk/meson/g12a.h
+++ b/drivers/clk/meson/g12a.h
@@ -70,6 +70,7 @@
 #define HHI_MALI_CLK_CNTL              0x1b0
 #define HHI_VPU_CLKC_CNTL              0x1b4
 #define HHI_VPU_CLK_CNTL               0x1bC
+#define HHI_ISP_CLK_CNTL               0x1C0
 #define HHI_NNA_CLK_CNTL               0x1C8
 #define HHI_HDMI_CLK_CNTL              0x1CC
 #define HHI_VDEC_CLK_CNTL              0x1E0