arm64: tegra: Fix GIC400 missing GICH/GICV register regions

GIC400 has full support for virtualization, and yet the tegra186
DT doesn't expose the GICH/GICV regions (despite exposing the
maintenance interrupt that only makes sense for virtualization).

Add the missing regions, based on the hunch that the HW doesn't
use the CPU build-in interfaces, but instead the external ones
provided by the GIC. KVM's virtual GIC now works with this change.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index a55d7ac95323d533846dd6f6670ed60c487d5d22..98544d16d01b7ddba4c4fc031256b405ab5b2919 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -845,7 +845,9 @@
                #interrupt-cells = <3>;
                interrupt-controller;
                reg = <0x0 0x03881000 0x0 0x1000>,
-                     <0x0 0x03882000 0x0 0x2000>;
+                     <0x0 0x03882000 0x0 0x2000>,
+                     <0x0 0x03884000 0x0 0x2000>,
+                     <0x0 0x03886000 0x0 0x2000>;
                interrupts = <GIC_PPI 9
                        (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
                interrupt-parent = <&gic>;