drm/amd/powerplay: drop unnecessary wrapper around pcie parameters setting

This can also help to maintain clear code layer.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index b0d863f4f55afc9be5183eff7ee19b0c1afc5da0..dbe5e97f77ca198a73e261d3bae16d548563ca84 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -33,6 +33,7 @@
 #include "navi10_ppt.h"
 #include "sienna_cichlid_ppt.h"
 #include "renoir_ppt.h"
+#include "amd_pcie.h"
 
 /*
  * DO NOT use these for err/warn/info/debug messages.
@@ -993,6 +994,7 @@ static int smu_sw_fini(void *handle)
 static int smu_smc_hw_setup(struct smu_context *smu)
 {
        struct amdgpu_device *adev = smu->adev;
+       uint32_t pcie_gen = 0, pcie_width = 0;
        int ret;
 
        if (smu_is_dpm_running(smu) && adev->in_suspend) {
@@ -1062,9 +1064,36 @@ static int smu_smc_hw_setup(struct smu_context *smu)
        if (!smu_is_dpm_running(smu))
                dev_info(adev->dev, "dpm has been disabled\n");
 
-       ret = smu_override_pcie_parameters(smu);
-       if (ret)
+       if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
+               pcie_gen = 3;
+       else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
+               pcie_gen = 2;
+       else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
+               pcie_gen = 1;
+       else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
+               pcie_gen = 0;
+
+       /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
+        * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
+        * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
+        */
+       if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
+               pcie_width = 6;
+       else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
+               pcie_width = 5;
+       else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
+               pcie_width = 4;
+       else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
+               pcie_width = 3;
+       else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
+               pcie_width = 2;
+       else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
+               pcie_width = 1;
+       ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
+       if (ret) {
+               dev_err(adev->dev, "Attempt to override pcie params failed!\n");
                return ret;
+       }
 
        ret = smu_enable_thermal_alert(smu);
        if (ret) {

diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index afd07c497205fd431bd6a937713992e32369d96c..3687e7620eb8389317782f06715888b883f30d26 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -2422,7 +2422,6 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
        .baco_exit = smu_v11_0_baco_exit,
        .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
        .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
-       .override_pcie_parameters = NULL,
        .set_df_cstate = arcturus_set_df_cstate,
        .allow_xgmi_power_down = arcturus_allow_xgmi_power_down,
        .log_thermal_throttling_event = arcturus_log_thermal_throttling_event,

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index c560c3d23581e3810f508322004f88f19bd93c17..7dd2aa9f2d1d707025788624236419535a5a7d19 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -568,7 +568,6 @@ struct pptable_funcs {
        int (*mode2_reset)(struct smu_context *smu);
        int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
        int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
-       int (*override_pcie_parameters)(struct smu_context *smu);
        int (*disable_umc_cdr_12gbps_workaround)(struct smu_context *smu);
        int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src);
        void (*log_thermal_throttling_event)(struct smu_context *smu);

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index b550cc837fe151fc44691eba9374384289bd8a20..ef319c7a1a37102ea410ce5b5bcc2554d637809d 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -270,8 +270,6 @@ int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
                                          uint32_t min,
                                          uint32_t max);
 
-int smu_v11_0_override_pcie_parameters(struct smu_context *smu);
-
 int smu_v11_0_set_performance_level(struct smu_context *smu,
                                    enum amd_dpm_forced_level level);
 

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 33b56f34ac427ee9ba0a22345ec5b727c7e4307e..1533559acd3c4f3354cdc01cc64c1a8ef4bdb5fd 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -2435,7 +2435,6 @@ static const struct pptable_funcs navi10_ppt_funcs = {
        .baco_exit = smu_v11_0_baco_exit,
        .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
        .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
-       .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
        .set_default_od_settings = navi10_set_default_od_settings,
        .od_edit_dpm_table = navi10_od_edit_dpm_table,
        .run_btc = navi10_run_btc,

diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 0a4f5fdc85f3bde8d8d8d6cc108fc0913dead524..4c9f75b77ba81952575a1d0dc59dad8cf619f285 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -2575,7 +2575,6 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
        .mode1_reset = smu_v11_0_mode1_reset,
        .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
        .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
-       .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
        .set_thermal_range = sienna_cichlid_set_thermal_range,
 };
 

diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h
index 727498a6e76d3c938b8df088e7f27ba6b8b3a66c..9a0660b0f7bc8c32aa4d01395ff31eb8acc9e7ce 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
+++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
@@ -90,7 +90,6 @@
 #define smu_get_dpm_ultimate_freq(smu, param, min, max)                        smu_ppt_funcs(get_dpm_ultimate_freq, 0, smu, param, min, max)
 #define smu_asic_set_performance_level(smu, level)                     smu_ppt_funcs(set_performance_level, -EINVAL, smu, level)
 #define smu_dump_pptable(smu)                                          smu_ppt_funcs(dump_pptable, 0, smu)
-#define smu_override_pcie_parameters(smu)                              smu_ppt_funcs(override_pcie_parameters, 0, smu)
 #define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap)  smu_ppt_funcs(update_pcie_parameters, 0, smu, pcie_gen_cap, pcie_width_cap)
 #define smu_set_thermal_range(smu, range)                              smu_ppt_funcs(set_thermal_range, 0, smu, range)
 #define smu_disable_umc_cdr_12gbps_workaround(smu)                     smu_ppt_funcs(disable_umc_cdr_12gbps_workaround, 0, smu)

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 234715a42b6cf6833bba5d38e53bf1bab3ccd10e..e1aebfc1ae8940f93c9a3dc35b93e399d1304b65 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -35,7 +35,6 @@
 #include "smu_v11_0.h"
 #include "soc15_common.h"
 #include "atom.h"
-#include "amd_pcie.h"
 #include "amdgpu_ras.h"
 
 #include "asic_reg/thm/thm_11_0_2_offset.h"
@@ -1840,47 +1839,6 @@ int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
        return ret;
 }
 
-int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
-{
-       struct amdgpu_device *adev = smu->adev;
-       uint32_t pcie_gen = 0, pcie_width = 0;
-       int ret;
-
-       if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
-               pcie_gen = 3;
-       else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
-               pcie_gen = 2;
-       else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
-               pcie_gen = 1;
-       else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
-               pcie_gen = 0;
-
-       /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
-        * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
-        * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
-        */
-       if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
-               pcie_width = 6;
-       else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
-               pcie_width = 5;
-       else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
-               pcie_width = 4;
-       else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
-               pcie_width = 3;
-       else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
-               pcie_width = 2;
-       else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
-               pcie_width = 1;
-
-       ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
-
-       if (ret)
-               dev_err(adev->dev, "[%s] Attempt to override pcie params failed!\n", __func__);
-
-       return ret;
-
-}
-
 int smu_v11_0_set_performance_level(struct smu_context *smu,
                                    enum amd_dpm_forced_level level)
 {